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    Error corrected quantum computer
    4.
    发明申请
    Error corrected quantum computer 有权

    公开(公告)号：US20080185576A1

    公开(公告)日：2008-08-07

    申请号：US11712639

    申请日：2007-03-01

    申请人： Lloyd Hollenberg ,  Ashley Stephens ,  Andrew Greentree ,  Austin Fowler ,  Cameron Wellard

    发明人： Lloyd Hollenberg ,  Ashley Stephens ,  Andrew Greentree ,  Austin Fowler ,  Cameron Wellard

    IPC分类号： H01L29/15

    CPC分类号： B82Y10/00 ,  G06N99/002

    摘要： This invention concerns quantum error correction, that is the correction of errors in the transport and processing of qubits, by use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site. The temporal process comprises the following steps: Creating a logical qubit in a section of the array by initialising an equal plurality of physical data and ancilla qubits at respective sites of the first and second lines within the section. Clocking each physical qubit site in the section at the same time. Permitting the physical data and ancilla qubits to move to an adjacent site in a clock cycle, provided that no site may contain more than one physical qubit at any time. Controlling the sites to achieve movement of ancilla qubits in the array to bring pairs of the ancilla qubits to respective first and second physical gate sites of logic function gates over the course of a number of clock cycles. Permitting logic operations to be performed at logic function gates which have both of their gate sites occupied by a physical ancilla qubit. Controlling the gate sites of the logic function gate to achieve the logic operation. Controlling the sites to achieve movement of the qubits in the array to bring pairs of all the data and ancilla qubits to respective logic function gates over the course of a number of clock cycles. Controlling the gate sites of the logic function gate to achieve the logic operation between each pair of data and ancilla qubits. Controlling the sites to achieve movement of the qubits in the array to bring all the data and ancilla qubits to respective sites where they can be read out. And, Using the values of the ancilla qubits read out to correct errors arising in the data qubits they have been gated with.

    Error corrected quantum computer
    6.
    发明授权
    Error corrected quantum computer 有权
    纠错量子计算机

    公开(公告)号：US07966549B2

    公开(公告)日：2011-06-21

    申请号：US11712639

    申请日：2007-03-01

    申请人： Lloyd Hollenberg ,  Ashley Stephens ,  Andrew Greentree ,  Austin Fowler ,  Cameron Wellard

    发明人： Lloyd Hollenberg ,  Ashley Stephens ,  Andrew Greentree ,  Austin Fowler ,  Cameron Wellard

    IPC分类号： H03M13/00

    CPC分类号： B82Y10/00 ,  G06N99/002

    摘要： The correction of errors in the transport and processing of qubits makes use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site. The temporal process comprises a number of steps to achieve movement of the qubits in the array to bring pairs of all the data and ancilla qubits to respective logic function gates over the course of a number of clock cycles. Then achieve the logic operation between each pair of data and ancilla qubits. Move the qubits in the array to bring all the data and ancilla qubits to respective sites where they can be read out. And, using the values of the ancilla qubits read out to correct errors arising in the data qubits they have been gated with.

    摘要翻译： 量子位传输和处理中的误差校正利用由多个物理量子位组成的逻辑量子位。 该过程发生在具有准二维拓扑的物理量子位位置的空间阵列上，所述准二维拓扑具有物理量子位址的第一行和物理量子位位置的第二行，其中第一和第二行并行排列， 第一行的网站在第二行的相应网站注册。 在物理量子位的第一和第二行之间是多个逻辑功能门，每个逻辑功能门由与第一行中的第一物理量子位址相关联的第一物理量子位门站和与物理量子位址相关联的第二物理量子位址组成 与第一个物理量子位网站对应的第二行的量子位网站。 时间过程包括实现阵列中的量子位的移动的许多步骤，以便在多个时钟周期的过程中将所有数据和辅助量子位的对成对到相应的逻辑功能门。 然后实现每对数据和辅助量子位之间的逻辑运算。 移动数组中的量子位将所有数据和辅助量子位传送到可以读出的各个站点。 并且，使用读出来的数字量子位的值来纠正在数据量子位中产生的错误。