公开(公告)号：US07952508B2

公开(公告)日：2011-05-31

申请号：US12553004

申请日：2009-09-02

申请人： Lorenzo Crespi ,  Ketan B Patel ,  Kyehyung Lee

发明人： Lorenzo Crespi ,  Ketan B Patel ,  Kyehyung Lee

IPC分类号： H03M1/66

CPC分类号： H03M1/066 ,  H03F3/217 ,  H03M1/822 ,  H03M3/502 ,  H03M7/3028 ,  H03M7/3037

摘要： Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.

摘要翻译： D类放大器已经从使用二进制脉宽调制（PWM）调制器演进到三电平PWM调制器。 用于音频应用的三级PWM驱动器提供消除音频系统输出的昂贵元素的优点。 然而，它们也引入增加的共模干扰。 三电平PWM产生三个状态，但是一个状态具有两个可互换的表示，其可被加扰以形成共模输出频谱。

公开(公告)号：US20110050467A1

公开(公告)日：2011-03-03

申请号：US12553004

申请日：2009-09-02

申请人： Lorenzo Crespi ,  Ketan B. Patel ,  Kyehyung Lee

发明人： Lorenzo Crespi ,  Ketan B. Patel ,  Kyehyung Lee

IPC分类号： H03M7/00

CPC分类号： H03M1/066 ,  H03F3/217 ,  H03M1/822 ,  H03M3/502 ,  H03M7/3028 ,  H03M7/3037

摘要： Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.

摘要翻译： D类放大器已经从使用二进制脉宽调制（PWM）调制器演进到三电平PWM调制器。 用于音频应用的三级PWM驱动器提供消除音频系统输出的昂贵元素的优点。 然而，它们也引入增加的共模干扰。 三电平PWM产生三个状态，但是一个状态具有两个可互换的表示，其可被加扰以形成共模输出频谱。

公开(公告)号：US20130200872A1

公开(公告)日：2013-08-08

申请号：US13755575

申请日：2013-01-31

申请人： Brian W. Friend ,  Kyehyung Lee

发明人： Brian W. Friend ,  Kyehyung Lee

IPC分类号： G05F1/10

CPC分类号： G05F1/10 ,  G05F3/24

摘要： A current comparator comprising a first NMOS transistor having a drain coupled to VDD, a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to VSS and a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to VDD, a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.

摘要翻译： 一种电流比较器，包括具有耦合到VDD的漏极，源极和栅极的第一NMOS晶体管。 第一PMOS晶体管，具有耦合到第一NMOS晶体管的源极以形成输入的源极，耦合到VSS的漏极和耦合到第一NMOS晶体管的栅极的栅极。 具有耦合到VDD的漏极，耦合到输入的源极和栅极的第二NMOS晶体管。 第一偏置电流源，其具有耦合到第二NMOS晶体管的源极的输入端和输出端。 第二偏置电流源具有耦合到第一NMOS晶体管的漏极的输入端和耦合到第一NMOS晶体管的栅极的输出。 第三NMOS晶体管，具有耦合到第一NMOS晶体管的栅极以形成输出，源极和栅极的漏极。