公开(公告)号：US20080263292A1

公开(公告)日：2008-10-23

申请号：US12123859

申请日：2008-05-20

申请人： Lorraine M. Herger ,  Mary McHugh ,  Dan E. Poff ,  Robert A. Saccone ,  Charles O. Schulz ,  T. Basil Smith

发明人： Lorraine M. Herger ,  Mary McHugh ,  Dan E. Poff ,  Robert A. Saccone ,  Charles O. Schulz ,  T. Basil Smith

IPC分类号： G06F12/00

CPC分类号： G06F12/08 ,  G06F13/1668 ,  G06F2212/401

摘要： In a computer system having an operating system and a compressed main memory defining a physical memory and a real memory characterized as an amount of main memory as seen by a processor, and including a compressed memory hardware controller device for controlling processor access to the compressed main memory, there is provided a system and method for managing real memory usage comprising: a compressed memory device driver for receiving real memory usage information from the compressed memory hardware controller, the information including a characterization of the real memory usage state: and, a compression management subsystem for monitoring the memory usage and initiating memory allocation and memory recovery in accordance with the memory usage state, the subsystem including mechanism for adjusting memory usage thresholds for controlling memory state changes. Such a system and method is implemented in software operating such that control of the real memory usage in the computer system is transparent to the operating system.

摘要翻译： 在具有操作系统和压缩主存储器的计算机系统中，所述操作系统和压缩主存储器限定物理存储器和实际存储器，其特征在于处理器所看到的主存储器的量，并且包括用于控制处理器访问压缩主体的压缩存储器硬件控制器设备 存储器，提供了一种用于管理实际存储器使用的系统和方法，包括：压缩存储器设备驱动器，用于从压缩存储器硬件控制器接收实际存储器使用信息，该信息包括实际存储器使用状态的表征;以及压缩 管理子系统，用于监视内存使用情况，并根据内存使用状态启动内存分配和内存恢复，该子系统包括调整用于控制内存状态更改的内存使用阈值的机制。 这样的系统和方法在软件操作中实现，使得对计算机系统中的实际存储器使用的控制对于操作系统是透明的。

公开(公告)号：US06681305B1

公开(公告)日：2004-01-20

申请号：US09584033

申请日：2000-05-30

申请人： Hubertus Franke ,  Bulent Abali ,  Lorraine M. Herger ,  Dan E. Poff ,  Robert A. Saccone, Jr. ,  T. Basil Smith

发明人： Hubertus Franke ,  Bulent Abali ,  Lorraine M. Herger ,  Dan E. Poff ,  Robert A. Saccone, Jr. ,  T. Basil Smith

IPC分类号： G06F1200

CPC分类号： G06F12/08 ,  G06F12/023 ,  G06F12/121 ,  G06F2212/401

摘要： In a system with hardware main memory compression, the method of this invention monitors the physical memory utilization and if physical memory is near exhaustion it forces memory to be paged out, thus freeing up real memory pages. These pages are then zeroed, thus they are highly compressible and therefore reduce the physical memory utilization. Pages that have been forced out due to high physical memory utilization are not made available for allocation. In systems where operating system changes are permitted, this invention dynamically controls the minimum size of the free page pool and zeros pages upon freeing. When the physical memory utilization falls below a critical threshold the mechanism reduces the minimum size of the free pool to allow further allocation. In systems where operating system changes are not possible, pages are allocated by a module (e.g. Device driver) and then zeroed. When the physical memory utilization falls below a critical threshold this method frees some of the explicitly set aside pages.

摘要翻译： 在具有硬件主存储器压缩的系统中，本发明的方法监视物理存储器利用率，并且如果物理存储器接近耗尽，则迫使存储器被分页出来，从而释放真实存储器页面。 这些页面然后归零，因此它们是高度可压缩的，因此减少物理内存利用率。 由于物理内存利用率高而被强制退出的页面不可用于分配。 在允许操作系统更改的系统中，本发明在释放时动态地控制自由页面池和零页面的最小尺寸。 当物理内存利用率低于临界阈值时，机制会降低可用池的最小大小以允许进一步分配。 在不可能进行操作系统更改的系统中，页面由模块（例如，设备驱动程序）分配，然后归零。 当物理内存利用率低于临界阈值时，此方法会释放某些明确设置的页面。

公开(公告)号：US07523290B2

公开(公告)日：2009-04-21

申请号：US10672376

申请日：2003-09-26

申请人： Peter A. Franaszek ,  Charles O. Schulz ,  T. Basil Smith ,  Robert B. Tremaine ,  Michael Wazlowski

发明人： Peter A. Franaszek ,  Charles O. Schulz ,  T. Basil Smith ,  Robert B. Tremaine ,  Michael Wazlowski

IPC分类号： G06F12/00

CPC分类号： G06F12/1009

摘要： A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.

摘要翻译： 一种计算系统和方法，所述计算系统和方法采用处理器设备来生成与实际存储器系统的存储器位置相关联的用于读取和写入数据的实际地址，所述系统包括：所述实际存储器系统中的用于存储数据的多个存储块， 用于存储包括一个或多个实际存储器块的数据页面的存储器存储器，每个实际存储器块被划分成一个或多个扇区，每个扇区包括物理存储器的连续字节; 物理存储器存储器中的转换表结构具有用于将实际地址与物理存储器的扇区相关联的条目，每个转换表条目包括用于指向其相关联的实际存储器块中的对应扇区的一个或多个指针， 用于由处理器发起的用于存储器读和写操作的一个或多个分配扇区中的数据; 以及用于直接操纵翻译表结构中的条目以执行页面操作而不实际访问物理存储器数据内容的控制装置。 在该系统中，操作所涉及的页面的实际数据从不被处理器访问，因此在存储器高速缓存层次结构中从不需要这样的数据，从而消除通常与这些块操作相关联的高速缓存损坏。 此外，翻译表的操作将涉及读取和写入几个字节以执行操作，而不是在被操纵的页面中读取和写入数百或数千字节。

公开(公告)号：US4239982A

公开(公告)日：1980-12-16

申请号：US915469

申请日：1978-06-14

申请人： T. Basil Smith ,  John R. Howatt ,  John F. McKenna, Jr.

发明人： T. Basil Smith ,  John R. Howatt ,  John F. McKenna, Jr.

IPC分类号： G06F1/12 ,  G06F11/18 ,  H04L7/00 ,  H03K3/00

CPC分类号： G06F11/1604 ,  G06F1/12 ,  G06F11/187 ,  H04L7/00

摘要： A fault-tolerant clock system for providng digital timing signals (system clock signals) is provided by a plurality of clock sources. Each clock source receives as inputs the generated clock signals from all the other clock sources and contains receiver circuitry to derive a system clock signal from said clock sources which is the consensus clock signals of the other sources. Each clock source generates and distributes to the other clock sources a clock signal which is phase locked to the derived system clock from its clock receiver. In a system of (2r+2) clock sources (r+2) of them will remain phase locked to each other despite up to r clock source failures. Any clock receiver responsive to any (2r+1) of the clock sources can therefore derive a correct system clock despite up to r clock source failures.

摘要翻译： 用于提供数字定时信号（系统时钟信号）的容错时钟系统由多个时钟源提供。 每个时钟源接收来自所有其他时钟源的所生成的时钟信号作为输入，并且包含从所述时钟源导出系统时钟信号的接收机电路，所述时钟源是其他源的一致时钟信号。 每个时钟源产生并分配给另一个时钟源，时钟信号与其时钟接收器被锁相到导出的系统时钟。 在（2r + 2）的时钟源（r + 2）的系统中，尽管达到时钟源故障，但是它们之间将保持相位锁定。 因此，任何响应任何（2r + 1）时钟源的时钟接收器都可能导致正确的系统时钟，尽管最多不能使用时钟源故障。

公开(公告)号：US5168495A

公开(公告)日：1992-12-01

申请号：US698685

申请日：1991-05-10

申请人： T. Basil Smith

发明人： T. Basil Smith

IPC分类号： G06F13/00 ,  H04L29/06

CPC分类号： H04L29/06

摘要： A nested frame communication protocol for communicating between computers. According to the nested frame communication protocol of the present invention, the computers communicate by transferring frames over communication links. The transmission of low priority frames may be interrupted in order to transmit high priority frames. After the transmission of the high priority frames is complete, the transmission of the low priority frames resumes. Processing states relating to interrupted frame transmissions are saved when the frame transmissions are interrupted. The processing states are restored when the interrupted frame transmissions are resumed.

摘要翻译： 用于在计算机之间通信的嵌套帧通信协议。 根据本发明的嵌套帧通信协议，计算机通过通过通信链路传送帧进行通信。 低优先级帧的传输可能被中断以便传送高优先级帧。 在高优先级帧的传输完成之后，恢复低优先级帧的传输。 当帧传输被中断时，与中断的帧传输相关的处理状态被保存。 当中断的帧传输被恢复时，恢复处理状态。

公开(公告)号：US4497059A

公开(公告)日：1985-01-29

申请号：US372734

申请日：1982-04-28

申请人： T. Basil Smith

发明人： T. Basil Smith

IPC分类号： G06F11/18

CPC分类号： G06F11/184 ,  G06F11/188 ,  G06F11/182

摘要： A system having a plurality of redundant channels operating in tight synchronism wherein input information received in one or more of said channels is distributed to all the other channels. The received information in each channel is retransmitted to suitable voter circuitry in each channel so as to provide one or more voted outputs in each channel based on the distributed and retransmitted information from all the channels. The voted outputs from all unfailed channels are substantially identical and the voted output from a failed channel will not be identical to that of the unfailed channels.

摘要翻译： 一种具有多个以紧密同步操作的冗余信道的系统，其中在一个或多个所述信道中接收的输入信息被分配给所有其他信道。 每个信道中的接收到的信息被重传到每个信道中的合适的选举电路，以便基于来自所有信道的分布和重传的信息在每个信道中提供一个或多个投票输出。 来自所有未通信频道的投票输出基本相同，失败频道的投票输出将与未通信频道的投票输出不一致。

公开(公告)号：US20080189392A1

公开(公告)日：2008-08-07

申请号：US12062211

申请日：2008-04-03

申请人： Alain Azagury ,  Michael Rodeh ,  Julian Satran ,  Ilan Shimony ,  T. Basil Smith ,  Dhruv M. Desai

发明人： Alain Azagury ,  Michael Rodeh ,  Julian Satran ,  Ilan Shimony ,  T. Basil Smith ,  Dhruv M. Desai

IPC分类号： G06F15/16

CPC分类号： H04L67/08 ,  H04L2212/00

摘要： A computer system includes a local area network (LAN) and a plurality of computers. Each of the computers includes at least one central processing unit (CPU) and a LAN interface, which is coupled to communicate over the LAN, while the computers include no on-board input/output (I/O) device controllers other than the LAN interface. One or more peripheral devices are coupled to communicate with the computers over the LAN.

摘要翻译： 计算机系统包括局域网（LAN）和多个计算机。 每个计算机包括至少一个中央处理单元（CPU）和LAN接口，其被耦合以通过LAN进行通信，而计算机不包括除LAN之外的板上输入/输出（I / O）设备控制器 接口。 一个或多个外围设备被耦合以通过LAN与计算机通信。