公开(公告)号：US20060109346A1

公开(公告)日：2006-05-25

申请号：US10992935

申请日：2004-11-19

申请人： John Robinson ,  Michael Wazlowski

发明人： John Robinson ,  Michael Wazlowski

IPC分类号： H04N7/18 ,  H04N9/47

CPC分类号： H04N21/4223 ,  H04N7/188 ,  H04N21/44218

摘要： A communication system for multiple users whereby an automatic indication of away status is prompted immediately upon a user's departure from the vicinity of a computer or other medium. In a preferred embodiment, this is accomplished, in an instant messaging environment, via a video camera arrangement whereby, upon there being a detection of a user's absence from the immediate vicinity, an automatic prompt is made to indicate away status for the user.

摘要翻译： 一种用于多个用户的通信系统，从而当用户离开计算机或其他介质的附近时立即提示离开状态的自动指示。 在优选实施例中，这在即时消息传送环境中经由摄像机装置来实现，由此，当检测到用户离开紧邻的不在时，自动提示用于指示用户的状态。

公开(公告)号：US06457104B1

公开(公告)日：2002-09-24

申请号：US09528688

申请日：2000-03-20

申请人： R. Brett Tremaine ,  Michael Wazlowski

发明人： R. Brett Tremaine ,  Michael Wazlowski

IPC分类号： G06F1200

CPC分类号： G06F12/08 ,  G06F12/023 ,  G06F12/0802 ,  G06F2212/401

摘要： In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies and, wherein information stored within the main memory is indirectly accessible by a processor through an uncompressed information cache, an improved memory architecture, apparatus and method for detecting and recovering the main memory space used to store “stale” information associated with cache lines in the “modified” state, and returning the storage to an unused pool for use in storing other information. This improves the overall compression rate of the system, thus lessening the likelihood of encountering a “memory pressure” situation where the system runs low on unused memory.

摘要翻译： 在具有主存储器的处理系统中，其中以压缩格式存储信息，以通过压缩效率获得额外的存储，并且其中存储在主存储器内的信息可由处理器通过未压缩信息高速缓存间接访问，改进的存储器 用于检测和恢复用于存储与“修改”状态的高速缓存行相关联的“过时”信息的主存储空间的结构，装置和方法，并将存储返回到未使用的池中以用于存储其他信息。 这提高了系统的整体压缩率，从而减少了在未使用的存储器上系统运行低的情况下遇到“存储器压力”的可能性。

公开(公告)号：US06665787B2

公开(公告)日：2003-12-16

申请号：US09795414

申请日：2001-02-28

申请人： Peter A. Franaszek ,  Charles O. Schulz ,  T. Basil Smith, III ,  Robert B. Tremaine ,  Michael Wazlowski

发明人： Peter A. Franaszek ,  Charles O. Schulz ,  T. Basil Smith, III ,  Robert B. Tremaine ,  Michael Wazlowski

IPC分类号： G06F1208

CPC分类号： G06F12/1009

摘要： A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.

公开(公告)号：US07523290B2

公开(公告)日：2009-04-21

申请号：US10672376

申请日：2003-09-26

申请人： Peter A. Franaszek ,  Charles O. Schulz ,  T. Basil Smith ,  Robert B. Tremaine ,  Michael Wazlowski

发明人： Peter A. Franaszek ,  Charles O. Schulz ,  T. Basil Smith ,  Robert B. Tremaine ,  Michael Wazlowski

IPC分类号： G06F12/00

CPC分类号： G06F12/1009

摘要： A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.

摘要翻译： 一种计算系统和方法，所述计算系统和方法采用处理器设备来生成与实际存储器系统的存储器位置相关联的用于读取和写入数据的实际地址，所述系统包括：所述实际存储器系统中的用于存储数据的多个存储块， 用于存储包括一个或多个实际存储器块的数据页面的存储器存储器，每个实际存储器块被划分成一个或多个扇区，每个扇区包括物理存储器的连续字节; 物理存储器存储器中的转换表结构具有用于将实际地址与物理存储器的扇区相关联的条目，每个转换表条目包括用于指向其相关联的实际存储器块中的对应扇区的一个或多个指针， 用于由处理器发起的用于存储器读和写操作的一个或多个分配扇区中的数据; 以及用于直接操纵翻译表结构中的条目以执行页面操作而不实际访问物理存储器数据内容的控制装置。 在该系统中，操作所涉及的页面的实际数据从不被处理器访问，因此在存储器高速缓存层次结构中从不需要这样的数据，从而消除通常与这些块操作相关联的高速缓存损坏。 此外，翻译表的操作将涉及读取和写入几个字节以执行操作，而不是在被操纵的页面中读取和写入数百或数千字节。

公开(公告)号：US20070088915A1

公开(公告)日：2007-04-19

申请号：US11250054

申请日：2005-10-13

申请人： Roch Archambault ,  Yaoqing Gao ,  Francis O' Connell ,  Robert Tremaine ,  Michael Wazlowski ,  Steven White ,  Lixin Zhang

发明人： Roch Archambault ,  Yaoqing Gao ,  Francis O' Connell ,  Robert Tremaine ,  Michael Wazlowski ,  Steven White ,  Lixin Zhang

IPC分类号： G06F13/00

CPC分类号： G06F9/3879 ,  G06F8/4442 ,  G06F9/30047 ,  G06F9/3455 ,  G06F12/0862 ,  G06F2212/6028

摘要： The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.

摘要翻译： 本发明提供了一种用于编译用于管理高速缓存系统的指令的计算机实现的方法，装置和计算机可用程序代码。 分析循环结构以识别指令中的缓存和预取条件的数据使用特征以形成识别的预取条件。 基于数据使用特性和识别的预取条件将一组控制指令插入到指令中以形成多个修改的指令。 编译多组修改指令的集合以生成用于执行的代码以形成编译指令。 编译指令中的一组控制指令形成高速缓存管理策略以在执行编译指令期间控制存储器系统中数据的移动。

公开(公告)号：US06549995B1

公开(公告)日：2003-04-15

申请号：US09478557

申请日：2000-01-06

申请人： Charles O. Schulz ,  T. Basil Smith, III ,  Robert B. Tremaine ,  Michael Wazlowski

发明人： Charles O. Schulz ,  T. Basil Smith, III ,  Robert B. Tremaine ,  Michael Wazlowski

IPC分类号： G06F1200

CPC分类号： G06F12/08 ,  G06F12/0292 ,  G06F2212/401

摘要： In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies and, wherein information stored within the main memory is indirectly accessible by a processor through a compression and decompression mechanisms, an improved memory architecture that accommodates the necessary compressed information data structures, together with a memory region and mapping method for storing information that bypasses the compression and decompression mechanisms to provide low latency processor access to certain address spaces.

摘要翻译： 在具有主存储器的处理系统中，其中以压缩格式存储信息，以通过压缩效率获得额外的存储，并且其中存储在主存储器内的信息可由处理器通过压缩和解压缩机制间接访问，改进的 存储器架构，其容纳必要的压缩信息数据结构，以及存储器区域和映射方法，用于存储绕过压缩和解压缩机制的信息，以提供对某些地址空间的低延迟处理器访问。