公开(公告)号：US5097422A

公开(公告)日：1992-03-17

申请号：US374485

申请日：1989-06-29

申请人： Ludlow V. Corbin, II ,  Steven G. Danielson ,  Richard E. Oettel ,  Mark E. Rossman ,  James E. Thiele

发明人： Ludlow V. Corbin, II ,  Steven G. Danielson ,  Richard E. Oettel ,  Mark E. Rossman ,  James E. Thiele

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method and apparatus for determining integrated circuit layouts from a virtual circuit description and specification of a technology. Starting with high-level descriptions of a circuit, a virtual geometric description of the circuit is developed using a virtual grid described in terms of reference points relative to a substrate surface. The relationships among the reference points are expressed as fractions of variables that can also be used to define the design rules. When the technology is specified, the relationships among the reference points is determined, as in the layout of the integrated circuit.

摘要翻译： 一种用于从虚拟电路描述和技术规范确定集成电路布局的方法和装置。 从电路的高级描述开始，利用相对于衬底表面的参考点描述的虚拟网格来开发电路的虚拟几何描述。 参考点之间的关系表示为也可用于定义设计规则的变量的分数。 当指定技术时，确定参考点之间的关系，如集成电路的布局。