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公开(公告)号：US08917133B2
公开(公告)日：2014-12-23
申请号：US14058302
申请日：2013-10-21
发明人： Chih-Jou Lin , Yuan-Hsun Chang , Cheng-Ji Chang , Ting-Chun Huang , Yu-Sheng Yi
CPC分类号： H03K3/64 , G06F1/0321 , G06F1/04 , H04L7/10
摘要： The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.
摘要翻译： 时钟生成方法包含以下步骤。 在脉冲识别步骤中，首先对输入脉冲信号进行滤波以去除更短的信号。 然后，对剩余的脉冲信号进行宽度数字化计算。 基于宽度数字化计算，记录信号并确定记录信号的周期。 期间的值被传递到增益模块。 在验证D / A转换器的输入值的步骤中，从增益模块向D / A转换器输入两个值，并将D / A转换器的输出传送到振荡器。 增益模块确定从增益模块到D / A转换器的所需输入值。 在脉冲产生步骤中，增益模块将期望的输入值输入到D / A转换器，D / A转换器又传送到振荡器以产生相应的时钟。
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公开(公告)号：US20140043082A1
公开(公告)日：2014-02-13
申请号：US14058302
申请日：2013-10-21
发明人： Chih-Jou Lin , Yuan-Hsun Chang , Cheng-Ji Chang , Ting-Chun Huang , Yu-Sheng Yi
IPC分类号： H03K3/64
CPC分类号： H03K3/64 , G06F1/0321 , G06F1/04 , H04L7/10
摘要： The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.
摘要翻译： 时钟生成方法包含以下步骤。 在脉冲识别步骤中，首先对输入脉冲信号进行滤波以去除更短的信号。 然后，对剩余的脉冲信号进行宽度数字化计算。 基于宽度数字化计算，记录信号并确定记录信号的周期。 期间的值被传递到增益模块。 在验证D / A转换器的输入值的步骤中，从增益模块向D / A转换器输入两个值，并将D / A转换器的输出传送到振荡器。 增益模块确定从增益模块到D / A转换器的所需输入值。 在脉冲产生步骤中，增益模块将期望的输入值输入到D / A转换器，D / A转换器又传送到振荡器以产生相应的时钟。
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