公开(公告)号：US11922294B2

公开(公告)日：2024-03-05

申请号：US16854564

申请日：2020-04-21

Applicant: ELEMENT AI INC.

Inventor： Boris Oreshkin ,  Dmitri Carpov

IPC: G06N3/06 ,  G06F1/03 ,  G06F17/18 ,  G06N3/045 ,  G06N3/063 ,  G06Q10/04

CPC classification number: G06N3/063 ,  G06F1/0321 ,  G06F17/18 ,  G06N3/045 ,  G06Q10/04

Abstract: Systems and components for use with neural networks. An execution block and a system architecture using that execution block are disclosed. The execution block uses a fully connected stack of layers and one output is a forecast for a time series while another output is a backcast that can be used to determine a residual from the input to the execution block. The execution block uses a waveform generator sub-unit whose parameters can be judiciously selected to thereby constrain the possible set of waveforms generated. By doing so, the execution block specializes its function. The system using the execution block has been shown to be better than the state of the art in providing solutions to the time series problem.

公开(公告)号：US10019027B2

公开(公告)日：2018-07-10

申请号：US15325855

申请日：2015-06-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Huagang Wu

IPC: G06F1/03 ,  H03L7/16

CPC classification number: G06F1/0321 ,  G06F1/022 ,  H03L7/16

Abstract: A direct digital frequency synthesis method comprises the following steps: calculating, by a phase accumulation module, a first phase according to a frequency synthesis word (S101); finding an amplitude value by a preset sinusoidal lookup table according to the first phase (S102); finding a second phase by a preset phase lookup table according to the amplitude value (S103); if the second phase is less than the first phase, adjusting and outputting the amplitude value (S105); or else, outputting the original amplitude value (S106); and performing, by a digital-to-analog converter, a digital-to-analog conversion according to the output amplitude value to obtain a sinusoidal wave (S107); wherein, for a N-bit phase accumulation module and a D-bit digital-to-analog converter, the preset phase lookup table has 2D−1-1 phase boundary value records corresponding to 0˜2D−1-2 amplitudes, each phase boundary value is stored in N-2 bits. A direct digital frequency synthesizer applying the above method is also disclosed.

公开(公告)号：US09876631B2

公开(公告)日：2018-01-23

申请号：US15085776

申请日：2016-03-30

Applicant: NXP B.V.

Inventor： Remco van de Beek ,  Jos Verlinden ,  Ghiath Al-kadi

IPC: H04L7/06 ,  H04L7/033 ,  G06F1/03 ,  H03L7/099 ,  H03L7/23 ,  H04B5/00 ,  H04L29/12

CPC classification number: H04L7/033 ,  G06F1/0321 ,  H03L7/0992 ,  H03L7/23 ,  H04B5/0031 ,  H04L61/1552

Abstract: A digital synchronizer is disclosed with a phase locked loop and a carrier generator. The phase locked loop is configured to produce an output signal having the same frequency as an input signal by selecting a divider ratio of a frequency divider with a control signal, the frequency divider divides the frequency of a high frequency signal by the divider ratio to provide the output signal; carrier generator is configured to generate an oversampled carrier signal by using the control signal to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal.

公开(公告)号：US09438259B2

公开(公告)日：2016-09-06

申请号：US14832342

申请日：2015-08-21

Applicant: Intel IP Corporation

Inventor： Stefan Tertinek ,  Peter Preyler ,  Thomas Mayer

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/82

CPC classification number: H03M1/10 ,  G06F1/0321 ,  H03L7/00 ,  H03L2207/50 ,  H03M1/82

Abstract: A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique.

Abstract translation: 根据示例的电路包括数字 - 时间转换器，其被配置为响应于控制信号接收振荡器信号并且基于接收的振荡器信号产生经处理的振荡器信号，以及时间交织控制电路，被配置为产生 基于时间交织技术的控制信号。

公开(公告)号：US09292035B2

公开(公告)日：2016-03-22

申请号：US14163600

申请日：2014-01-24

Applicant: Andrew Thomas

Inventor： Andrew Thomas

IPC: G06F1/02 ,  G06F1/03 ,  G01N27/90

CPC classification number: G06F1/0321 ,  G01N27/9046 ,  G06F1/022 ,  G06F17/5045

Abstract: Disclosed are a method of and an apparatus devising a packet based DDS circuitry for performing packet based a direct digital synthesizing (DDS) function within an electronic testing instrument. The circuitry comprising a DDS logic circuit configured to execute direct digital syntheses on a plurality of consecutive packets of sine-like waves, each packet having a length of a period precisely chosen such that the sine wave at the end of one packet matches up with the sine wave at the start of the immediate subsequent packet. Also disclosed is an eddy current testing circuitry using multiple outputs of the single packet based DDS, one of the output is used in a circuit producing reference signals approximating the response signals. With the usage of the packet based DDS, the reference signal can be highly effective in nulling the unchanging portion of the response signals.

Abstract translation: 公开了一种设计基于分组的DDS电路的方法和装置，用于基于电子测试仪器内的直接数字合成（DDS）功能执行分组。 该电路包括DDS逻辑电路，该DDS逻辑电路经配置以在正弦波的多个连续分组上执行直接数字合成，每个分组具有精确选择的周期的长度，使得一个分组结束时的正弦波与 正弦波在即时后续数据包的开始。 还公开了使用基于单个分组的DDS的多个输出的涡流测试电路，其中一个输出用于产生近似响应信号的参考信号。 通过使用基于分组的DDS，参考信号可以在使响应信号的不变部分归零时非常有效。

公开(公告)号：US20140250424A1

公开(公告)日：2014-09-04

申请号：US14197002

申请日：2014-03-04

Applicant: TOTAL RESOURCE MANAGEMENT, INC.

Inventor： Albert M. JOHNSON, JR. ,  Andrew Joseph MAHEN

IPC: G06F9/44

CPC classification number: G06F8/33 ,  G06F1/022 ,  G06F1/0321

Abstract: A method includes: displaying an editor of an integrated development environment executed by a computing system; receiving an input command from a user; detecting existence or absence of text preceding a cursor position in the editor; identifying at least one completion attribute, the at least one attribute being based on content of text preceding the cursor position if existence of text is detected, or the editor if absence of text is detected; transmitting the identified at least one attribute to a server configured to execute asset management software; receiving a plurality of completion values from the server based on the identified at least one attribute; storing the received plurality of completion values; and displaying, for selection by the user, the plurality of completion values at the cursor position in the editor.

Abstract translation: 一种方法包括：显示由计算系统执行的集成开发环境的编辑器; 从用户接收输入命令; 检测编辑器中光标位置之前的文本是否存在; 识别至少一个完成属性，所述至少一个属性基于如果检测到文本的存在，则基于光标位置之前的文本的内容，或者如果检测不到文本，则编辑器; 将所识别的至少一个属性发送到被配置为执行资产管理软件的服务器; 基于所识别的至少一个属性从服务器接收多个完成值; 存储所接收的多个完成值; 并显示用户选择编辑器中光标位置处的多个完成值。

公开(公告)号：US20140175891A1

公开(公告)日：2014-06-26

申请号：US14107399

申请日：2013-12-16

Applicant: IMEC

Inventor： Sunyoung Kim ,  Refet Firat Yazicioglu

IPC: H02J3/00

CPC classification number: H02J3/00 ,  G06F1/022 ,  G06F1/0321 ,  Y10T307/724

Abstract: A current generator is disclosed. An example current generator includes a plurality of current cells connected in parallel, each current cell being connected to a switch. The current generator further includes a first summer configured to sum the output of each current cell of a first subset of the plurality of current cells and a second summer configured to sum the output of each current cell of a second subset of the plurality of current cells. The current generator also includes a combiner configured to combine the outputs of the first and second summers. Further, each switch is switchable according to a sequence to generate a summed output of the current cells at a plurality of quantization levels to generate positive and/or negative alternations of a pseudo-sinusoidal, alternating current.

Abstract translation: 公开了一种电流发生器。 示例性电流发生器包括并联连接的多个电流单元，每个电流单元连接到开关。 电流发生器还包括第一加法器，其被配置为对多个当前单元的第一子集的每个当前单元的输出进行求和，第二加法器被配置为对多个当前单元的第二子集的每个当前单元的输出求和 。 电流发生器还包括组合器，其被配置为组合第一和第二加法器的输出。 此外，每个开关可以根据序列切换，以产生多个量化级别的当前单元的相加输出，以产生伪正弦交流电流的正和/或负变化。

公开(公告)号：US20130249625A1

公开(公告)日：2013-09-26

申请号：US13754917

申请日：2013-01-31

Applicant: ADVANTEST CORPORATION

Inventor： Kiyotaka ICHIYAMA

IPC: H03K3/013 ,  H03H11/04

CPC classification number: H03K3/013 ,  G06F1/0321 ,  G06F2211/902 ,  H03H11/04

Abstract: In order to output an accurate waveform in which quantization noise has been cancelled out, provided is a signal generating apparatus that outputs an output signal corresponding to a waveform data sequence expressing a waveform, the signal generating apparatus comprising a DA converting section that outputs an analog signal by sequentially performing digital/analog conversion on each piece of data included in the waveform data sequence, at a timing of a sampling clock; and a jitter injecting section that injects jitter decreasing a quantization noise component of the output signal, into the sampling clock supplied to the DA converting section.

Abstract translation: 为了输出消除了量化噪声的精确波形，提供了一种信号发生装置，其输出与表示波形的波形数据序列对应的输出信号，该信号发生装置包括DA转换部分，其输出模拟 在采样时钟的定时，对包括在波形数据序列中的每条数据进行顺序执行数字/模拟转换; 以及抖动注入部分，其向提供给DA转换部分的采样时钟中注入降低输出信号的量化噪声分量的抖动。

公开(公告)号：US08483341B2

公开(公告)日：2013-07-09

申请号：US12340639

申请日：2008-12-19

Applicant: Yasuhiko Miki ,  Hideaki Okuda

Inventor： Yasuhiko Miki ,  Hideaki Okuda

IPC: H04L7/00

CPC classification number: G06F1/0321 ,  G01R31/31922

Abstract: A signal generation system maintains a phase relationship between output signals of first and second signal generators even when the sampling clock frequency is changed. The signal generators are coupled via a communication means including a dedicated cable where the delay amount of the communication means is known and fixed. The first signal generator provides sampling clock, sequence clock and trigger/event signals to the second signal generator and CPUs of the generators share information via the cable. When the frequency of the sampling clock is changed, the CPU of the first or second signal generator calculates the clock number of the frequency changed sampling clock equivalent to the delay amount of the communication means. A delay circuit of the first signal generator 100 delays the waveform data by one sampling clock based on the calculated value for adjusting phase relationship between the waveform data in the signal generators 1.

Abstract translation: 即使采样时钟频率发生变化，信号发生系统也保持第一和第二信号发生器的输出信号之间的相位关系。 信号发生器通过包括通信装置的延迟量已知和固定的专用电缆的通信装置耦合。 第一信号发生器向第二信号发生器提供采样时钟，序列时钟和触发/事件信号，并且发生器的CPU通过电缆共享信息。 当采样时钟的频率改变时，第一或第二信号发生器的CPU计算与通信装置的延迟量相当的频率改变采样时钟的时钟数。 第一信号发生器100的延迟电路基于用于调整信号发生器1中的波形数据之间的相位关系的计算值，将波形数据延迟一个采样时钟。

公开(公告)号：US08238390B2

公开(公告)日：2012-08-07

申请号：US12782470

申请日：2010-05-18

Applicant: Pascal Deladurantaye ,  Louis Desbiens ,  Yves Taillon ,  Dany Lemieux ,  Brian W. Baird

Inventor： Pascal Deladurantaye ,  Louis Desbiens ,  Yves Taillon ,  Dany Lemieux ,  Brian W. Baird

IPC: H01S3/10

CPC classification number: B23K26/0624 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  G06F1/0321 ,  H01S3/2308 ,  H01S5/06216 ,  H01S5/06821 ,  H01S5/146

Abstract: Methods stabilize the output of a pulsed laser system using pulse shaping capabilities. In some embodiments, transient effects following a transition between a QCW regime and a pulse shaping regime are mitigated by ensuring that the average QCW optical power substantially corresponds to the average pulsed optical power outputted in a steady-state operation of the pulsed laser system in the pulse shaping regime. The QCW signal or the pulse shaping signal may be adapted for this purpose. In other embodiments, transient effects associated with non-process pulses emitted between series of consecutive process pulses are mitigated through the proper use of sequential pulse shaping.

Abstract translation: 方法使用脉冲整形功能来稳定脉冲激光系统的输出。 在一些实施例中，通过确保平均QCW光功率基本上对应于在脉冲激光系统的稳态操作中输出的平均脉冲光功率，可以减轻QCW状态和脉冲整形状态之间的转变之后的瞬态效应 脉冲整形方式。 QCW信号或脉冲整形信号可以适用于此目的。 在其他实施例中，通过适当地使用顺序脉冲整形来减轻与在连续过程脉冲串之间发射的非过程脉冲相关的瞬态效应。