公开(公告)号：US20210126047A1

公开(公告)日：2021-04-29

申请号：US17078240

申请日：2020-10-23

Applicant: MACROBLOCK, INC. ,  FORCE MOS TECHNOLOGY CO., LTD.

Inventor： Kao-Way Tu ,  Yuan-Shun Chang ,  Li-Chang Yang ,  Yi-Sheng Lin

IPC: H01L27/15

Abstract: A metal-oxide semiconductor module includes multiple metal-oxide semiconductor components separated from one another by at least one first trench. Each of the metal-oxide semiconductor components includes a heavily doped semiconductor layer which includes a drain region, an epitaxial layer which is formed with an indentation such that the drain region is partially exposed from the epitaxial layer, and a metallic patterned contact unit. The epitaxial layer also includes a source region and a gate region that are spaced-apart formed therein. The metallic patterned contact unit includes source, gate, and drain patterned contacts which are electrically connected to the source, gate, and drain regions, respectively. A light-emitting diode display device including the metal-oxide semiconductor module is also disclosed.

公开(公告)号：US11450708B2

公开(公告)日：2022-09-20

申请号：US17078240

申请日：2020-10-23

Applicant: MACROBLOCK, INC. ,  FORCE MOS TECHNOLOGY CO., LTD.

Inventor： Kao-Way Tu ,  Yuan-Shun Chang ,  Li-Chang Yang ,  Yi-Sheng Lin

IPC: H01L27/15

Abstract: A metal-oxide semiconductor module includes multiple metal-oxide semiconductor components separated from one another by at least one first trench. Each of the metal-oxide semiconductor components includes a heavily doped semiconductor layer which includes a drain region, an epitaxial layer which is formed with an indentation such that the drain region is partially exposed from the epitaxial layer, and a metallic patterned contact unit. The epitaxial layer also includes a source region and a gate region that are spaced-apart formed therein. The metallic patterned contact unit includes source, gate, and drain patterned contacts which are electrically connected to the source, gate, and drain regions, respectively. A light-emitting diode display device including the metal-oxide semiconductor module is also disclosed.

公开(公告)号：US20200251468A1

公开(公告)日：2020-08-06

申请号：US16600738

申请日：2019-10-14

Applicant: Force MOS Technology Co., Ltd.

Inventor： Kao-Way Tu ,  Yuan-Shun CHANG

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L23/535

Abstract: A metal-oxide-semiconductor (MOS) device comprising a heavily doped substrate, epitaxialan layer, an open, a plurality of MOS units, and a metal pattern layer is provided. The epitaxial layer is formed on the heavily doped substrate. The open is defined in the epitaxial layer to expose the heavily doped substrate. The MOS units are formed on the epitaxial layer. The metal pattern layer comprises a source metal pattern, a gate metal pattern, and a drain metal pattern. The source metal pattern and the gate metal pattern are formed on the epitaxial layer. The drain metal pattern fills in the open and is extended from the heavily doped substrate upward to above the epitaxial layer.

公开(公告)号：US20200105890A1

公开(公告)日：2020-04-02

申请号：US16244395

申请日：2019-01-10

Applicant: Force MOS Technology Co., Ltd.

Inventor： Kao-Way Tu ,  Po-An Tsai ,  Huan-Chung Weng

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/78

Abstract: A fabricating method of a shielded gate MOSFET is provided, including steps of: forming a semiconductor substrate having a trench; forming a sacrifice oxide layer in the trench, the sacrifice oxide layer covering a side wall of the trench; forming a source polycrystalline silicon region in the trench; forming an insulation oxide layer above the source polycrystalline silicon region to have the source polycrystalline silicon region fully enclosed by the sacrifice oxide layer and the insulation oxide layer; depositing polycrystalline silicon into the trench and carrying out a back etching to control a thickness of the insulation oxide layer above the source polycrystalline silicon region; forming a gate oxide layer in the trench, the gate oxide layer covering the side wall of the trench; forming a gate polycrystalline silicon region in the trench; and forming a body layer and a heavily doped region around the trench in an ion implantation manner.

公开(公告)号：US11056488B2

公开(公告)日：2021-07-06

申请号：US16600738

申请日：2019-10-14

Applicant: Force MOS Technology Co., Ltd.

Inventor： Kao-Way Tu ,  Yuan-Shun Chang

IPC: H01L27/088 ,  H01L23/535 ,  H01L29/417 ,  H01L29/423

Abstract: A metal-oxide-semiconductor (MOS) device comprising a heavily doped substrate, an epitaxial layer, an open, a plurality of MOS units, and a metal pattern layer is provided. The epitaxial layer is formed on the heavily doped substrate. The open is defined in the epitaxial layer to expose the heavily doped substrate. The MOS units are formed on the epitaxial layer. The metal pattern layer comprises a source metal pattern, a gate metal pattern, and a drain metal pattern. The source metal pattern and the gate metal pattern are formed on the epitaxial layer. The drain metal pattern fills in the open and is extended from the heavily doped substrate upward to above the epitaxial layer.

公开(公告)号：US10700175B2

公开(公告)日：2020-06-30

申请号：US16244395

申请日：2019-01-10

Applicant: Force MOS Technology Co., Ltd.

Inventor： Kao-Way Tu ,  Po-An Tsai ,  Huan-Chung Weng

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40

Abstract: A fabricating method of a shielded gate MOSFET is provided, includes the steps of forming a semiconductor substrate having a trench, forming a sacrifice oxide layer in the trench, the sacrifice oxide layer covering a side wall of the trench, forming a source polycrystalline silicon region in the trench, forming an insulation oxide layer above the source polycrystalline silicon region to have the source polycrystalline silicon region fully enclosed by the sacrifice oxide layer and the insulation oxide layer, depositing polycrystalline silicon into the trench and carrying out a back etching to control a thickness of the insulation oxide layer above the source polycrystalline silicon region, forming a gate oxide layer in the trench, the gate oxide layer covering the side wall of the trench, forming a gate polycrystalline silicon region in the trench, and forming a body layer and a heavily doped region around the trench in an ion implantation manner.