公开(公告)号：US10475492B1

公开(公告)日：2019-11-12

申请号：US16047550

申请日：2018-07-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shang-Chi Yang ,  Chun-Yu Liao ,  Yi-Wei Chang

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06

Abstract: A memory device comprises an array of memory cells, and a plurality of sense amplifiers coupled with the memory cells. A controller is configured to execute a read operation in response to a command and address, including a read cycle in which the memory cells at the address are electrically coupled to the sense amplifiers, and in which the memory cells at the address are electrically decoupled from the sense amplifiers in response to a timing signal.