Abstract:
A wireless data transceiver includes a media access controller (MAC) that receives an inbound packet from an air interface and to buffer that packet for transport to a host, and receives an outbound packet and transfers that packet to the air interface. A host interface receives the inbound packet from the MAC and transfers the inbound packet to the host, and receives the outbound packet from the host for transfer to the MAC. Transport controller circuitry (TCC), including processing circuitry configured to execute instructions, manages the transceiver. Hardware data transport circuitry (HDTC) for transporting packets in either direction between the MAC and the host interface includes a buffer memory having a plurality of slots. The TCC or HDTC issues a start or stop signal to the host interface causing the HDTC and the host interface to begin or end transfer of data between the buffer memory and the host interface.
Abstract:
Methods, systems and computer program products are described for transferring aggregated data packets over an I/O interface from a host to a multiport embedded device. For example, a method includes receiving, by the device from the host, a single write command that (i) specifies two or more ports from among multiple ports of the device, and (ii) includes two or more data packets to be respectively written to the specified ports. The multiple ports of the device are mapped to corresponding locations of memory of the device. The method further includes saving, by the device in response to the single write command, the two or more data packets at two or more memory locations to which the specified ports are mapped. Additionally, the method includes sending, upon saving the data packets, a single notification to the host indicating that the device is ready to receive another write command.