公开(公告)号：US08817916B1

公开(公告)日：2014-08-26

申请号：US14065003

申请日：2013-10-28

Applicant: Marvell International Ltd.

Inventor： Konstantinos Sarrigeorgidis ,  Yanni Chen ,  Leilei Song ,  Kedar Shirali

IPC: H04L27/00

CPC classification number: H04L25/067 ,  H03M13/612 ,  H04L1/0045 ,  H04L25/03286 ,  H04L27/2647

Abstract: Methods and apparatus are provided for performing log-likelihood ratio (LLR) computations in a pipeline. Portions of a metric used to compute LLR values are computed in one pipeline part. The portions correspond to all permutations of some received signal streams. The portions are combined with one permutation x2 of the received signal stream that was not included in the previous pipeline computation in a subsequent pipeline part to produce M values associated with a particular bit position. At each subsequent clock cycle, a different permutation of x2 is combined with the previously computed portions producing different M values. State values corresponding to different values of bit positions of the received stream are computed by finding the minimum among the M values, in each clock cycle, that affect a particular bit position. The state values are combined to compute the LLR values for the bit position in a final pipeline part.

Abstract translation: 提供了在流水线中执行对数似然比（LLR）计算的方法和装置。 用于计算LLR值的度量的部分在一个管道部分中计算。 这些部分对应于一些接收的信号流的所有排列。 这些部分与接收信号流的一个置换x2组合在一起，该置换x2未被包括在随后的流水线部分中的先前流水线计算中，以产生与特定位位置相关联的M个值。 在每个随后的时钟周期，x2的不同置换与先前计算的产生不同M值的部分组合。 通过在每个时钟周期内找到影响特定位位置的M个值中的最小值来计算对应于接收流的比特位置的不同值的状态值。 组合状态值以计算最终流水线部分中位位置的LLR值。

公开(公告)号：US09164959B1

公开(公告)日：2015-10-20

申请号：US13741141

申请日：2013-01-14

Applicant: MARVELL INTERNATIONAL LTD.

Inventor： Yanni Chen ,  Rajesh Juluri

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: A discrete Fourier transform calculation apparatus includes a plurality of multiplier units, and a plurality of butterfly calculation units. Each butterfly calculation unit is configured to perform simultaneous calculations for at least two stages of a fast Fourier transform (FFT) algorithm by using shared resources of the butterfly calculation unit. Each butterfly calculation unit includes a respective memory device to store input data for the corresponding at least two stages of the FFT algorithm, and a respective butterfly calculator coupled to the respective memory device. Each butterfly calculation unit also includes a respective controller coupled to the respective memory device and the respective butterfly calculator. The respective controller is configured to control the corresponding butterfly calculation unit to calculate the corresponding at least two stages of the FFT algorithm. The plurality of butterfly calculation units and the plurality of multiplier units are coupled in series.

Abstract translation: 离散傅里叶变换计算装置包括多个乘法器单元和多个蝶形计算单元。 每个蝶形计算单元被配置为通过使用蝶形计算单元的共享资源来执行快速傅里叶变换（FFT）算法的至少两个级的同时计算。 每个蝶形计算单元包括相应的存储器件，用于存储用于FFT算法的对应的至少两个级的输入数据，以及耦合到相应的存储器件的相应的蝶形计算器。 每个蝶形计算单元还包括耦合到相应存储器件和相应蝶形计算器的相应控制器。 相应的控制器被配置为控制相应的蝶形计算单元来计算相应的FFT算法的至少两个阶段。 多个蝶形计算单元和多个乘法器单元串联耦合。