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    Method and system for forward error correction decoding based on a revised error channel estimate
    6.
    发明授权
    Method and system for forward error correction decoding based on a revised error channel estimate 有权
    基于修正误差信道估计的前向纠错解码方法和系统

    公开(公告)号：US09564921B1

    公开(公告)日：2017-02-07

    申请号：US14613805

    申请日：2015-02-04

    申请人： PMC-SIERRA US, INC.

    发明人： Peter Graumann ,  Sean Gibb

    IPC分类号： H03M13/11

    CPC分类号： H03M13/1125 ,  H03M13/1111 ,  H03M13/1131 ,  H03M13/114 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/612 ,  H03M13/6325

    摘要： An FEC codeword comprises channel information indicating the reliability of the information contained by the FEC codeword. The channel information can be used to generate an initial error channel estimate. Based on the initial error channel estimate, an FEC decoder can decode the FEC codeword to increase the reliability of the information contained by the FEC codeword. According to the present disclosure, a method and system of decoding comprises: comparing a current codeword to a previous codeword in order to identify bits corrected between the previous and current codewords; revising an error channel estimate based on the identified corrected bits, the revised estimate representing a change in the error channel over time; and decoding the codeword based on the revised error channel estimate.

    摘要翻译： FEC码字包括指示由FEC码字包含的信息的可靠性的信道信息。 信道信息可用于产生初始误差信道估计。 基于初始误差信道估计，FEC解码器可以对FEC码字进行解码，以增加FEC码字所包含的信息的可靠性。 根据本公开，解码方法和系统包括：将当前码字与先前码字进行比较，以便识别在先前和当前码字之间校正的比特; 基于所识别的校正比特来修正误差信道估计，修正的估计表示误差信道随时间的变化; 以及基于经修改的误差信道估计对码字进行解码。

    Method and device for measuring the current signal-to-noise ratio when decoding LDPC codes
    7.
    发明授权
    Method and device for measuring the current signal-to-noise ratio when decoding LDPC codes 有权
    用于在解码LDPC码时测量当前信噪比的方法和装置

    公开(公告)号：US09503219B2

    公开(公告)日：2016-11-22

    申请号：US14331175

    申请日：2014-07-14

    申请人： Topcon Positioning Systems, Inc.

    发明人： Nikolay Vazhenin ,  Andrey Veitsel ,  Ivan Kirianov

    IPC分类号： H03M13/00 ,  H04L1/00 ,  H04L1/20 ,  H03M13/11 ,  H04B17/336

    CPC分类号： H03M13/612 ,  H03M13/1111 ,  H03M13/33 ,  H04B17/336 ,  H04L1/005 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/0063 ,  H04L1/20

    摘要： A method for measuring a signal-to-noise ratio when decoding Low Density Parity Check (LDPC) codes is provided. The method includes receiving from an input of a demodulator an input code word with “strong” or “weak” solutions, decoding the input code word in a LDPC decoder using a predetermined dependence of a mean number of iterations on the signal-to-noise ratio, recording a number of iterations performed during the decoding of the input code word, averaging derived values of the number of iterations for a specified time interval, estimating a signal-to-noise ratio based on averaged derived values of the number of iterations and based on the predetermined dependence of the mean number of iterations on the signal-to-noise ratio, and generating an output decoded code word.

    摘要翻译： 提供了一种在解码低密度奇偶校验（LDPC）码时测量信噪比的方法。 该方法包括从解调器的输入端接收具有“强”或“弱”解的输入码字，使用平均迭代次数对信号噪声的预定依赖性对LDPC解码器中的输入码字进行解码 记录在输入代码字的解码期间执行的迭代次数，平均在特定时间间隔内的迭代次数的导出值，基于迭代次数的平均导出值估计信噪比，以及 基于平均迭代次数对信噪比的预定依赖性，并且生成输出解码码字。

    Dynamic log likelihood ratio quantization for solid state drive controllers
    8.
    发明授权
    Dynamic log likelihood ratio quantization for solid state drive controllers 有权
    固态驱动控制器的动态对数似然比量化

    公开(公告)号：US09450619B2

    公开(公告)日：2016-09-20

    申请号：US13853282

    申请日：2013-03-29

    申请人： LSI Corporation

    发明人： Yunxiang Wu ,  Erich F. Haratsch

    IPC分类号： G11C29/00 ,  H03M13/45 ,  G06F11/10 ,  H03M13/37 ,  H03M13/00 ,  H03M13/11

    CPC分类号： H03M13/45 ,  G06F11/1064 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/612 ,  H03M13/6577 ,  H03M13/658

    摘要： A method for system for dynamic channel Log Likelihood Ratio (LLR) quantization for a Solid State Drive (SSD) controller is a targeted approach to scaling which results in a scaled, quantized set of LLRs whose relative magnitude remains undisturbed from an original magnitude. The method reads a set of voltages from each channel of the SSD. The set of reads is configured in location and number for performance. Once a set is returned, the method determines an LLR for each of the voltages read resulting in a raw set of LLRs. Targeted scaling results in a scaled set of LLRs between an upper limit and a lower limit determined for reading by a decoder. Once scaled, the LLRs are rounded and quantized for use by the decoder to produce an Error Correction Code (ECC).

    摘要翻译： 用于固态驱动（SSD）控制器的用于动态信道对数似然比（LLR）量化的系统的方法是缩放的目标方法，其导致缩放的量化的LLR集合，其相对幅度保持不受原始幅度的干扰。 该方法从SSD的每个通道读取一组电压。 读取集合的位置和数量被配置为执行性能。 一旦返回一个集合，该方法确定读取的每个电压的LLR，从而产生一组原始的LLR。 目标缩放导致为解码器读取确定的上限和下限之间的缩放的LLR集合。 一旦缩放，LLR被舍入和量化以供解码器使用以产生纠错码（ECC）。

    System and method for lifetime specific LDPC decoding
    9.
    发明授权
    System and method for lifetime specific LDPC decoding 有权
    寿命特定LDPC解码的系统和方法

    公开(公告)号：US09397701B1

    公开(公告)日：2016-07-19

    申请号：US13792831

    申请日：2013-03-11

    申请人： Microsemi Storage Solutions (US), Inc.

    发明人： Rino Micheloni ,  Peter Z. Onufryk ,  Alessia Marelli ,  Christopher I. W. Norrie

    IPC分类号： H03M13/37 ,  H03M13/11 ,  G06F11/10 ,  H03M13/13

    CPC分类号： H03M13/13 ,  G06F11/1012 ,  G11C2211/5634 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/612

    摘要： A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of lifetime specific LLR look-up tables representative of the lifetime threshold voltage distribution of the memory storage module, wherein each of the plurality of lifetime specific LLR look-up tables comprises a plurality of LLRs representative of a specific point in the lifetime of the memory storage module for each of the plurality of soft-decision bits. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

    摘要翻译： 提供了一种非易失性存储器存储控制器，用于将对数似然比（LLR）传送到用于LDPC编码码字的解码中的低密度奇偶校验（LDPC）解码器。 控制器包括用于使用多个软判决参考电压读取存储在非易失性存储器存储模块中的LDPC编码码字的读取电路，以提供表示代码字的多个软判决位。 控制器还包括表示存储器存储模块的寿命阈值电压分布的多个寿命特定的LLR查找表，其中多个寿命特定的LLR查找表中的每一个包括表示特定点的多个LLR 在多个软判决位中的每一个的存储器存储模块的寿命期内。 控制器将来自适当的LLR查找表的LLR提供给用于码字的后续解码的LDPC解码器。