公开(公告)号：US20160261260A1

公开(公告)日：2016-09-08

申请号：US14922202

申请日：2015-10-26

Applicant: MEDIATEK INC.

Inventor： Bo-Jyun Kuo ,  An-Siou Li

IPC: H03K5/24

CPC classification number: H03K5/2481 ,  H03K19/018528

Abstract: An input buffer circuit comprising: a first current source; a first differential control circuit, configured to generate a first bias voltage at the first couple terminal according to the input signals, and configured to generate first control signals according to the input signals; a second current source; a second differential control circuit, configured to generate a second bias voltage at the second couple terminal according to the input signals, and configured to generate second control signals according to the input signals; a third current source, configured to provide a first current according to the second bias voltage; a first differential output circuit, configured to receive the first control signals to generate output signals; a fourth current source, configured to drain a second current according to the first bias voltage; and a second differential output circuit, configured to receive the second control signals to generate the output signal.

Abstract translation: 一种输入缓冲电路，包括：第一电流源; 第一差分控制电路，被配置为根据输入信号在第一耦合端产生第一偏置电压，并且被配置为根据输入信号产生第一控制信号; 第二个电流源; 第二差分控制电路，被配置为根据输入信号在第二耦合端产生第二偏置电压，并且被配置为根据输入信号产生第二控制信号; 第三电流源，被配置为根据所述第二偏置电压提供第一电流; 第一差分输出电路，被配置为接收所述第一控制信号以产生输出信号; 第四电流源，被配置为根据所述第一偏置电压漏极第二电流; 以及第二差分输出电路，被配置为接收所述第二控制信号以产生所述输出信号。

公开(公告)号：US09590607B2

公开(公告)日：2017-03-07

申请号：US14922202

申请日：2015-10-26

Applicant: MEDIATEK INC.

Inventor： Bo-Jyun Kuo ,  An-Siou Li

IPC: H03K3/00 ,  H03K5/24

CPC classification number: H03K5/2481 ,  H03K19/018528

Abstract: An input buffer circuit comprising: a first current source; a first differential control circuit, configured to generate a first bias voltage at the first couple terminal according to the input signals, and configured to generate first control signals according to the input signals; a second current source; a second differential control circuit, configured to generate a second bias voltage at the second couple terminal according to the input signals, and configured to generate second control signals according to the input signals; a third current source, configured to provide a first current according to the second bias voltage; a first differential output circuit, configured to receive the first control signals to generate output signals; a fourth current source, configured to drain a second current according to the first bias voltage; and a second differential output circuit, configured to receive the second control signals to generate the output signal.

Abstract translation: 一种输入缓冲电路，包括：第一电流源; 第一差分控制电路，被配置为根据输入信号在第一耦合端产生第一偏置电压，并且被配置为根据输入信号产生第一控制信号; 第二个电流源; 第二差分控制电路，被配置为根据输入信号在第二耦合端产生第二偏置电压，并且被配置为根据输入信号产生第二控制信号; 第三电流源，被配置为根据所述第二偏置电压提供第一电流; 第一差分输出电路，被配置为接收所述第一控制信号以产生输出信号; 第四电流源，被配置为根据所述第一偏置电压漏极第二电流; 以及第二差分输出电路，被配置为接收所述第二控制信号以产生所述输出信号。