公开(公告)号：US20160173093A1

公开(公告)日：2016-06-16

申请号：US14830755

申请日：2015-08-20

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  An-Siou Li

IPC: H03K19/0175

CPC classification number: H03K19/017509 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018507

Abstract: A method for performing signal driving control in an electronic device and an associated apparatus are provided. The method includes: generating a first driving control signal and a second driving control signal according to a data signal, wherein the second driving control signal transits in response to a transition of the data signal, and the first driving control signal includes a pulse corresponding to the transition of the data signal; and utilizing a first switching unit to control a first signal path between a first voltage level and an output terminal of an output stage according to the first driving control signal, and utilizing a second switching unit to control a second signal path between the first voltage level and the output terminal according to the second driving control signal, wherein a first impedance of the first signal path is less than a second impedance of the second signal path.

Abstract translation: 提供了一种在电子设备和相关设备中执行信号驱动控制的方法。 该方法包括：根据数据信号产生第一驱动控制信号和第二驱动控制信号，其中第二驱动控制信号响应于数据信号的转变而转换，并且第一驱动控制信号包括对应于 数据信号的转换; 以及利用第一开关单元根据第一驱动控制信号来控制输出级的第一电压电平和输出端之间的第一信号路径，并且利用第二开关单元来控制第一电压电平 以及根据第二驱动控制信号的输出端子，其中第一信号路径的第一阻抗小于第二信号路径的第二阻抗。

公开(公告)号：US20160261260A1

公开(公告)日：2016-09-08

申请号：US14922202

申请日：2015-10-26

Applicant: MEDIATEK INC.

Inventor： Bo-Jyun Kuo ,  An-Siou Li

IPC: H03K5/24

CPC classification number: H03K5/2481 ,  H03K19/018528

Abstract: An input buffer circuit comprising: a first current source; a first differential control circuit, configured to generate a first bias voltage at the first couple terminal according to the input signals, and configured to generate first control signals according to the input signals; a second current source; a second differential control circuit, configured to generate a second bias voltage at the second couple terminal according to the input signals, and configured to generate second control signals according to the input signals; a third current source, configured to provide a first current according to the second bias voltage; a first differential output circuit, configured to receive the first control signals to generate output signals; a fourth current source, configured to drain a second current according to the first bias voltage; and a second differential output circuit, configured to receive the second control signals to generate the output signal.

Abstract translation: 一种输入缓冲电路，包括：第一电流源; 第一差分控制电路，被配置为根据输入信号在第一耦合端产生第一偏置电压，并且被配置为根据输入信号产生第一控制信号; 第二个电流源; 第二差分控制电路，被配置为根据输入信号在第二耦合端产生第二偏置电压，并且被配置为根据输入信号产生第二控制信号; 第三电流源，被配置为根据所述第二偏置电压提供第一电流; 第一差分输出电路，被配置为接收所述第一控制信号以产生输出信号; 第四电流源，被配置为根据所述第一偏置电压漏极第二电流; 以及第二差分输出电路，被配置为接收所述第二控制信号以产生所述输出信号。

公开(公告)号：US20170040995A1

公开(公告)日：2017-02-09

申请号：US15183804

申请日：2016-06-16

Applicant: MEDIATEK INC.

Inventor： An-Siou Li ,  Shang-Pin Chen

IPC: H03K17/687

CPC classification number: H03K17/687 ,  G11C5/14 ,  G11C7/1057 ,  G11C7/1069 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: An apparatus for performing signal driving in an electronic device may include a decoupling capacitor and at least one switching unit (e.g. one or more switching units). The decoupling capacitor may have a first terminal and a second terminal, and may be positioned in an output stage within the electronic device and coupled between a first predetermined voltage level and another predetermined voltage level, where the apparatus may perform signal driving with aid of the output stage. In addition, the aforementioned at least one switching unit may be coupled between one terminal of the first and the second terminals of the decoupling capacitor and at least one of the first predetermined voltage level and the other predetermined voltage level, and may be arranged for selectively disabling the decoupling capacitor.

Abstract translation: 用于在电子设备中执行信号驱动的设备可以包括去耦电容器和至少一个开关单元（例如一个或多个开关单元）。 去耦电容器可以具有第一端子和第二端子，并且可以位于电子设备内的输出级中并且耦合在第一预定电压电平和另一预定电压电平之间，其中该装置可以借助于 输出阶段。 此外，上述至少一个开关单元可以耦合在去耦电容器的第一端子和第二端子的一个端子和第一预定电压电平和另一预定电压电平中的至少一个之间，并且可以被布置成选择性地 禁用去耦电容。

公开(公告)号：US09590607B2

公开(公告)日：2017-03-07

申请号：US14922202

申请日：2015-10-26

Applicant: MEDIATEK INC.

Inventor： Bo-Jyun Kuo ,  An-Siou Li

IPC: H03K3/00 ,  H03K5/24

CPC classification number: H03K5/2481 ,  H03K19/018528

Abstract: An input buffer circuit comprising: a first current source; a first differential control circuit, configured to generate a first bias voltage at the first couple terminal according to the input signals, and configured to generate first control signals according to the input signals; a second current source; a second differential control circuit, configured to generate a second bias voltage at the second couple terminal according to the input signals, and configured to generate second control signals according to the input signals; a third current source, configured to provide a first current according to the second bias voltage; a first differential output circuit, configured to receive the first control signals to generate output signals; a fourth current source, configured to drain a second current according to the first bias voltage; and a second differential output circuit, configured to receive the second control signals to generate the output signal.

Abstract translation: 一种输入缓冲电路，包括：第一电流源; 第一差分控制电路，被配置为根据输入信号在第一耦合端产生第一偏置电压，并且被配置为根据输入信号产生第一控制信号; 第二个电流源; 第二差分控制电路，被配置为根据输入信号在第二耦合端产生第二偏置电压，并且被配置为根据输入信号产生第二控制信号; 第三电流源，被配置为根据所述第二偏置电压提供第一电流; 第一差分输出电路，被配置为接收所述第一控制信号以产生输出信号; 第四电流源，被配置为根据所述第一偏置电压漏极第二电流; 以及第二差分输出电路，被配置为接收所述第二控制信号以产生所述输出信号。

公开(公告)号：US09473142B2

公开(公告)日：2016-10-18

申请号：US14830755

申请日：2015-08-20

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  An-Siou Li

IPC: G11C7/10 ,  H03K19/0175

CPC classification number: H03K19/017509 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018507

Abstract: A method for performing signal driving control in an electronic device and an associated apparatus are provided. The method includes: generating a first driving control signal and a second driving control signal according to a data signal, wherein the second driving control signal transits in response to a transition of the data signal, and the first driving control signal includes a pulse corresponding to the transition of the data signal; and utilizing a first switching unit to control a first signal path between a first voltage level and an output terminal of an output stage according to the first driving control signal, and utilizing a second switching unit to control a second signal path between the first voltage level and the output terminal according to the second driving control signal, wherein a first impedance of the first signal path is less than a second impedance of the second signal path.

Abstract translation: 提供了一种在电子设备和相关设备中执行信号驱动控制的方法。 该方法包括：根据数据信号产生第一驱动控制信号和第二驱动控制信号，其中第二驱动控制信号响应于数据信号的转变而转换，并且第一驱动控制信号包括对应于 数据信号的转换; 以及利用第一开关单元根据第一驱动控制信号来控制输出级的第一电压电平和输出端之间的第一信号路径，并且利用第二开关单元来控制第一电压电平 以及根据第二驱动控制信号的输出端子，其中第一信号路径的第一阻抗小于第二信号路径的第二阻抗。

公开(公告)号：US20160173085A1

公开(公告)日：2016-06-16

申请号：US14746856

申请日：2015-06-23

Applicant: Mediatek Inc.

Inventor： Chen-Feng Chiang ,  An-Siou Li

IPC: H03K17/687 ,  H03K17/693

CPC classification number: H03K17/6871 ,  H03K17/08142 ,  H03K17/693 ,  H03K19/0027 ,  H03K19/00384 ,  H03K19/018521

Abstract: An I/O driving circuit comprising a post driver. The post driver comprises: a first switch device, comprising a first terminal coupled to an I/O voltage, and comprising a second terminal, wherein the first switch device provides an initial driving voltage at the second terminal of the first switch device; and a first voltage providing device, comprising a first terminal coupled to the second terminal of the first switch device, and comprising a second terminal. The first voltage providing device is configured to provide a driving voltage at the second terminal of the first voltage providing device via providing a voltage drop to the initial driving voltage.

Abstract translation: 一种包括后置驱动器的I / O驱动电路。 所述后驱动器包括：第一开关装置，包括耦合到I / O电压的第一端子，并且包括第二端子，其中所述第一开关装置在所述第一开关装置的所述第二端子处提供初始驱动电压; 以及第一电压提供装置，包括耦合到第一开关装置的第二端子的第一端子，并且包括第二端子。 第一电压提供装置被配置为通过向初始驱动电压提供电压降来在第一电压提供装置的第二端提供驱动电压。

公开(公告)号：US10128841B2

公开(公告)日：2018-11-13

申请号：US15685028

申请日：2017-08-24

Applicant: MEDIATEK INC.

Inventor： An-Siou Li

IPC: H03K19/00 ,  H04B1/16

Abstract: A termination circuit, a receiver and associated terminating method are provided. The termination circuit is applied to a receiving terminal for receiving a channel transmission signal. Being coupled to a control module, the termination circuit includes an upper circuit and a lower circuit. The upper circuit selectively conducts the receiving terminal to a first voltage terminal, and the lower circuit selectively conducts the receiving terminal to a second voltage terminal. The control module detects a voltage level of the receiving terminal in response to a trigger signal, and accordingly controls the first switching signal and the second switching signal for a termination duration. The termination duration is corresponding to an n-th data bit carried by the channel transmission signal.

公开(公告)号：US10027321B2

公开(公告)日：2018-07-17

申请号：US14746856

申请日：2015-06-23

Applicant: MEDIATEK INC.

Inventor： Chen-Feng Chiang ,  An-Siou Li

IPC: H03K17/0814 ,  H03K17/687 ,  H03K19/0185 ,  H03K17/693 ,  H03K19/00 ,  H03K19/003

Abstract: An I/O driving circuit comprising a post driver. The post driver comprises: a first switch device, comprising a first terminal coupled to an I/O voltage, and comprising a second terminal, wherein the first switch device provides an initial driving voltage at the second terminal of the first switch device; and a first voltage providing device, comprising a first terminal coupled to the second terminal of the first switch device, and comprising a second terminal. The first voltage providing device is configured to provide a driving voltage at the second terminal of the first voltage providing device via providing a voltage drop to the initial driving voltage.

公开(公告)号：US20180083623A1

公开(公告)日：2018-03-22

申请号：US15685028

申请日：2017-08-24

Applicant: MEDIATEK INC.

Inventor： An-Siou Li

IPC: H03K19/00 ,  H04B1/16

CPC classification number: H03K19/0005 ,  H04B1/16

Abstract: A termination circuit, a receiver and associated terminating method are provided. The termination circuit is applied to a receiving terminal for receiving a channel transmission signal. Being coupled to a control module, the termination circuit includes an upper circuit and a lower circuit. The upper circuit selectively conducts the receiving terminal to a first voltage terminal, and the lower circuit selectively conducts the receiving terminal to a second voltage terminal. The control module detects a voltage level of the receiving terminal in response to a trigger signal, and accordingly controls the first switching signal and the second switching signal for a termination duration. The termination duration is corresponding to an n-th data bit carried by the channel transmission signal.

公开(公告)号：US09825627B2

公开(公告)日：2017-11-21

申请号：US15183804

申请日：2016-06-16

Applicant: MEDIATEK INC.

Inventor： An-Siou Li ,  Shang-Pin Chen

IPC: H03K3/00 ,  H03K17/687 ,  G11C5/14 ,  G11C7/10 ,  G11C29/02 ,  G11C29/04

CPC classification number: H03K17/687 ,  G11C5/14 ,  G11C7/1057 ,  G11C7/1069 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: An apparatus for performing signal driving in an electronic device may include a decoupling capacitor and at least one switching unit (e.g. one or more switching units). The decoupling capacitor may have a first terminal and a second terminal, and may be positioned in an output stage within the electronic device and coupled between a first predetermined voltage level and another predetermined voltage level, where the apparatus may perform signal driving with aid of the output stage. In addition, the aforementioned at least one switching unit may be coupled between one terminal of the first and the second terminals of the decoupling capacitor and at least one of the first predetermined voltage level and the other predetermined voltage level, and may be arranged for selectively disabling the decoupling capacitor.