公开(公告)号：US20190123176A1

公开(公告)日：2019-04-25

申请号：US16121730

申请日：2018-09-05

申请人： MEDIATEK Inc.

发明人： Cheng-Tien WAN ,  Yao-Tsung HUANG ,  Yun-San HUANG ,  Ming-Cheng LEE ,  Wei-Che HUANG

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84

摘要： A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

公开(公告)号：US20220406921A1

公开(公告)日：2022-12-22

申请号：US17821195

申请日：2022-08-22

申请人： MEDIATEK Inc.

发明人： Cheng-Tien WAN ,  Yao-Tsung HUANG ,  Yun-San HUANG ,  Ming-Cheng LEE ,  Wei-Che HUANG

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

摘要： A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

公开(公告)号：US20210135016A1

公开(公告)日：2021-05-06

申请号：US17025095

申请日：2020-09-18

申请人： MEDIATEK INC.

发明人： Cheng-Tien WAN ,  Ming-Cheng LEE

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

摘要： A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.