公开(公告)号：US20180293026A1

公开(公告)日：2018-10-11

申请号：US15935200

申请日：2018-03-26

Applicant: MEDIATEK INC.

Inventor： Bo-Wei HSIEH ,  Chia-Yu CHAN ,  Shang-Pin CHEN

IPC: G06F3/06

Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.

公开(公告)号：US20200058335A1

公开(公告)日：2020-02-20

申请号：US16540156

申请日：2019-08-14

Applicant: MEDIATEK INC.

Inventor： Bo-Wei HSIEH ,  Chia-Yu CHAN ,  Jou-Ling CHEN

IPC: G11C7/22 ,  G11C7/10

Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.