公开(公告)号：US20180293026A1

公开(公告)日：2018-10-11

申请号：US15935200

申请日：2018-03-26

Applicant: MEDIATEK INC.

Inventor： Bo-Wei HSIEH ,  Chia-Yu CHAN ,  Shang-Pin CHEN

IPC: G06F3/06

Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.

公开(公告)号：US20230289063A1

公开(公告)日：2023-09-14

申请号：US18170096

申请日：2023-02-16

Applicant: MEDIATEK INC.

Inventor： Bo-Wei HSIEH ,  Chen-Chieh WANG ,  Szu-Ying CHENG ,  Jou-Ling CHEN

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: An electronic system is provided. A memory device includes a plurality of bank groups. A controller is coupled to the memory device and includes a request queue. The request queue is configured to store a plurality of requests. When the requests correspond to the different bank groups, the controller is configured to access data of the memory device according to a plurality of long burst commands corresponding to the requests. When the requests correspond to the same bank group, the controller is configured to access the data of the memory device according to a plurality of short burst commands corresponding to the requests. The short burst commands correspond to a short burst length, and the long burst commands correspond to a long burst length. The long burst length is twice the short burst length. The memory device is a low-power double data rate synchronous dynamic random access memory.

公开(公告)号：US20180005689A1

公开(公告)日：2018-01-04

申请号：US15702845

申请日：2017-09-13

Applicant: MediaTek Inc.

Inventor： Bo-Wei HSIEH

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/419 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G11C7/109 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/419 ,  G11C2207/2281 ,  G11C2207/229

Abstract: An operating method for a dynamic random access memory (DRAM) obtains a plurality of first sub-commands of a first activate command via a command bus, and obtaining a plurality of first address information regarding a plurality of first portions of a first row address of a specific bank via an address bus. Each of the first sub-commands corresponds to an individual first portion of the first row address of the specific bank. The method further combines the first portions of the first row address of the specific bank in response to a specific sub-command of the first sub-commands, so as to obtain a first complete row address; and obtains an access command via the command bus.

公开(公告)号：US20200058335A1

公开(公告)日：2020-02-20

申请号：US16540156

申请日：2019-08-14

Applicant: MEDIATEK INC.

Inventor： Bo-Wei HSIEH ,  Chia-Yu CHAN ,  Jou-Ling CHEN

IPC: G11C7/22 ,  G11C7/10

Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.

公开(公告)号：US20190074051A1

公开(公告)日：2019-03-07

申请号：US15995187

申请日：2018-06-01

Applicant: MEDIATEK INC.

Inventor： Chia-Fu CHANG ,  Hsiang-I HUANG ,  Bo-Wei HSIEH ,  Szu-Ying CHENG ,  Yu-Hsien TSAI

IPC: G11C11/406

Abstract: A refresh control method for a memory system is provided. The memory system includes a dynamic random access memory with a register set and a memory cell array. The refresh control method includes the following steps. Firstly, a masking command or an unmasking command is issued, and thus the register set is updated. A first region of the memory cell array is set as a masked region according to the masking command. A second region of the memory cell array is set as an unmasked region according to the unmasking command. Then, a refresh command is issued to the dynamic random access memory. According to the refresh command, a refresh action is performed on the second region of the memory cell array.

公开(公告)号：US20180204610A1

公开(公告)日：2018-07-19

申请号：US15862884

申请日：2018-01-05

Applicant: MEDIATEK INC.

Inventor： Bo-Wei HSIEH ,  Ching-Yeh HSUAN ,  Shang-Pin CHEN

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C7/109 ,  G11C7/1093 ,  G11C11/408 ,  G11C11/4093 ,  G11C2207/2254

Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.