公开(公告)号：US20240422382A1

公开(公告)日：2024-12-19

申请号：US18336274

申请日：2023-06-16

Applicant: MEDIATEK INC.

Inventor： You-Tsai JENG ,  Yi-Cheng CHEN ,  Kuo-Chang CHENG ,  Kai-Wen YEH ,  Chih-Wei CHOU ,  Chia-Hao CHANG ,  Chi-Chih CHEN ,  Yu-Sung CHANG ,  Chin-Lung LIN ,  Ko-Yin LAI ,  Tai-Lai TUNG

IPC: H04N21/4363

Abstract: A clock control method for a High Definition Multimedia Interface (HDMI) receiver operating in a power-saving mode in a sink device is provided. The HDMI receiver has a first module, a second module, and a third module. The clock control method includes the following stages. A clock signal is enabled to be sent to the first module and the third module during a first region of received data. The clock signal is disabled to be sent to the second module during the first region of the received data. The clock signal is enabled to be sent to the third module and the clock signal is disabled to be sent to the first module and the second module during a second region of the received data.