公开(公告)号：US10932358B2

公开(公告)日：2021-02-23

申请号：US16114669

申请日：2018-08-28

Applicant: MEDIATEK INC.

Inventor： Duen-Yi Ho ,  Hung-Chuan Chen ,  Shang-Pin Chen

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/498 ,  G06F13/40 ,  H01L23/538 ,  H01L23/50

Abstract: A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.

公开(公告)号：US12300679B2

公开(公告)日：2025-05-13

申请号：US17739295

申请日：2022-05-09

Applicant: MEDIATEK INC.

Inventor： Yi-Jyun Lee ,  Duen-Yi Ho ,  Hsing-Chih Liu ,  Che-Hung Kuo

IPC: H01L23/48 ,  H01L23/498 ,  H01L25/16 ,  H01L49/02 ,  H01L23/00

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.

公开(公告)号：US10679949B2

公开(公告)日：2020-06-09

申请号：US15411077

申请日：2017-01-20

Applicant: MEDIATEK INC.

Inventor： Sheng-Mou Lin ,  Duen-Yi Ho

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L23/528

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.