公开(公告)号：US20180332252A1

公开(公告)日：2018-11-15

申请号：US15806718

申请日：2017-11-08

Applicant: MEDIATEK INC.

Inventor： Wei-Ting WANG ,  Han-Lin LI ,  Yu-Jen CHEN ,  Yu-Ming LIN

IPC: H04N7/01

CPC classification number: H04N7/0127 ,  G09G5/005 ,  G09G2340/0435 ,  G09G2350/00 ,  G09G2360/08

Abstract: An image processing apparatus including first circuitry, second circuitry, third circuitry, and fourth circuitry is provided. The first circuitry determines a frame miss rate according to a current frame rate and a target frame rate of an image signal. The second circuitry decreases the target frame rate to the current frame rate when the frame miss rate is greater than a first threshold. The third circuitry increases the target frame rate to an upper-limit frame rate which is determined according to the frame rendering time or memory bandwidth capability, when the frame miss rate is less than a second threshold which is smaller than the first threshold. The fourth circuitry applies the decreased or increased target frame rate for an image to be displayed.