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公开(公告)号：US20220166412A1
公开(公告)日：2022-05-26
申请号：US17504485
申请日：2021-10-18
申请人： MEDIATEK INC.
发明人： Shou-En Liu , Wen-Sung Chiang , Ming-Han Hsieh , Keng-Jui Chang , Lin-Chien Chen
摘要： A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.
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公开(公告)号：US11611334B2
公开(公告)日：2023-03-21
申请号：US17504485
申请日：2021-10-18
申请人： MEDIATEK INC.
发明人： Shou-En Liu , Wen-Sung Chiang , Ming-Han Hsieh , Keng-Jui Chang , Lin-Chien Chen
摘要： A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.
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