公开(公告)号：US10910320B2

公开(公告)日：2021-02-02

申请号：US16129751

申请日：2018-09-12

Applicant: MEDIATEK INC.

Inventor： Shi-Bai Chen

IPC: H01L23/552 ,  H01L49/02 ,  H01L23/522

Abstract: A shielded metal-oxide-metal (MOM) capacitor includes a substrate, a lower shielding plate disposed on the substrate and in parallel with a major surface of the substrate, an upper shielding plate situated above the lower shielding plate and in parallel with the lower shielding plate, and a middle plate sandwiched between the lower shielding plate and the upper shielding plate. The middle plate includes two parallel first connecting bars extending along a first direction, a plurality of first fingers extending between the two parallel first connecting bars along a second direction, and an electrode strip spaced apart from and surrounded by the two parallel first connecting bars and the first fingers.

公开(公告)号：US20240038647A1

公开(公告)日：2024-02-01

申请号：US18215830

申请日：2023-06-29

Applicant: MEDIATEK INC.

Inventor： Wei-Chih Chen ,  Shi-Bai Chen

IPC: H01L23/498 ,  H10B80/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H10B80/00 ,  H01L25/18 ,  H01L24/13 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204

Abstract: A semiconductor package includes a partitioned package substrate composed of substrate parts arranged in a side-by-side manner; an integrated circuit die mounted on a first surface of the partitioned package substrate; and solder balls mounted on a second surface of the partitioned package substrate opposite to the first surface.

公开(公告)号：US20190164903A1

公开(公告)日：2019-05-30

申请号：US16129751

申请日：2018-09-12

Applicant: MEDIATEK INC.

Inventor： Shi-Bai Chen

IPC: H01L23/552 ,  H01L49/02

Abstract: A shielded metal-oxide-metal (MOM) capacitor includes a substrate, a lower shielding plate disposed on the substrate and in parallel with a major surface of the substrate, an upper shielding plate situated above the lower shielding plate and in parallel with the lower shielding plate, and a middle plate sandwiched between the lower shielding plate and the upper shielding plate. The middle plate includes two parallel first connecting bars extending along a first direction, a plurality of first fingers extending between the two parallel first connecting bars along a second direction, and an electrode strip spaced apart from and surrounded by the two parallel first connecting bars and the first fingers.

公开(公告)号：US20240038648A1

公开(公告)日：2024-02-01

申请号：US18216561

申请日：2023-06-29

Applicant: MEDIATEK INC.

Inventor： Wei-Chih Chen ,  Shi-Bai Chen

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49833 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/13 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/13147

Abstract: A semiconductor package includes a partitioned package substrate that is composed of multiple discrete substrates arranged in a side-by-side manner. The discrete substrates include a central substrate and peripheral substrates surrounding the central substrate. At least one integrated circuit die is mounted on a first surface of the partitioned package substrate. A plurality of solder balls is mounted on a second surface of the partitioned package substrate opposite to the first surface.

公开(公告)号：US20160027772A1

公开(公告)日：2016-01-28

申请号：US14337216

申请日：2014-07-22

Applicant: MEDIATEK INC.

Inventor： Shi-Bai Chen ,  Tung-Hsing Lee

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated capacitor includes a semiconductor substrate comprising a trench isolation area; a first interlayer dielectric (ILD) layer covering the trench isolation area; a first electrode plate comprising at least a first contact layer in the first ILD layer, wherein the contact layer is disposed directly on the trench isolation area; a second electrode plate in the first ILD layer; and a capacitor dielectric structure between the first electrode plate and the second electrode plate.

Abstract translation: 集成电容器包括：半导体衬底，包括沟槽隔离区域; 覆盖所述沟槽隔离区域的第一层间电介质层（ILD）层; 所述第一电极板包括所述第一ILD层中的至少第一接触层，其中所述接触层直接设置在所述沟槽隔离区域上; 第一ILD层中的第二电极板; 以及在所述第一电极板和所述第二电极板之间的电容器电介质结构。