Abstract:
A critical path emulating apparatus includes a critical path emulator (CPE) and an interconnection circuit. The CPE is capable of emulating a critical path of a target device, and supporting a plurality of speed information detection modes. The interconnection circuit is capable of supporting a plurality of interconnection arrangements, wherein when the interconnection circuit is configured to have a first interconnection arrangement, the CPE is capable of being used in a first speed information detection mode, and when the interconnection circuit is configured to have a second interconnection arrangement, the CPE is capable of being used in a second speed information detection mode.