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    METHOD AND COMPUTER-READABLE MEDIUM FOR DYNAMICALLY MANAGING POWER OF MULTI-CORE PROCESSOR
    3.
    发明申请
    METHOD AND COMPUTER-READABLE MEDIUM FOR DYNAMICALLY MANAGING POWER OF MULTI-CORE PROCESSOR 有权
    用于动态管理多核处理器功能的方法和计算机可读介质

    公开(公告)号：US20160062447A1

    公开(公告)日：2016-03-03

    申请号：US14811851

    申请日：2015-07-29

    Applicant: Mediatek Inc.

    Inventor： Jih-Ming Hsu ,  Wen-Tsan Hsieh ,  Che-Ming Hsu ,  Yeh-Ji Chou ,  Jen-Chieh Yang ,  Shih-Yen Chiu ,  Wan-Ching Huang ,  Ming-Hsien Lee

    IPC: G06F1/32

    CPC classification number: G06F1/3243 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: A method and a computer-readable medium for dynamically managing power of a multi-core processor of a computing system are provided. The multi-core processor generates a dynamic voltage and frequency scaling (DVFS) table, determines a first index by alternatively selecting either a power budget or a required performance thereof, determines a current thread level parallelism (TLP) of the computing system, selects one of entries according to the current TLP and the first index, and configure first cores and second cores thereof according to a first settings and a second settings of the selected entry.

    Abstract translation: 提供了一种用于动态管理计算系统的多核处理器的功率的方法和计算机可读介质。 多核处理器生成动态电压和频率缩放（DVFS）表，通过交替地选择功率预算或其所需性能来确定第一索引，确定计算系统的当前线程级并行度（TLP），选择一个 根据当前TLP和第一索引的条目，并且根据所选择的条目的第一设置和第二设置来配置第一核心和第二核心。

    Apparatus and method for controlling multi-core processor of computing system
    4.
    发明授权
    Apparatus and method for controlling multi-core processor of computing system 有权

    公开(公告)号：US10031574B2

    公开(公告)日：2018-07-24

    申请号：US14845879

    申请日：2015-09-04

    Applicant: MediaTek Inc.

    Inventor： Jih-Ming Hsu ,  Yen-Lin Lee ,  Jia-Ming Chen ,  Shih-Yen Chiu ,  Chung-Ho Chang ,  Ya-Ting Chang ,  Ming-Hsien Lee

    IPC: G06F1/32

    Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.

    MULTI-CHANNEL MEMORY SYSTEM USING ASYMMETRIC CHANNEL FREQUENCY SCALING AND RELATED POWER MANAGEMENT METHOD
    5.
    发明申请
    MULTI-CHANNEL MEMORY SYSTEM USING ASYMMETRIC CHANNEL FREQUENCY SCALING AND RELATED POWER MANAGEMENT METHOD 有权
    使用不对称通道频率分级和相关电源管理方法的多通道存储器系统

    公开(公告)号：US20160125923A1

    公开(公告)日：2016-05-05

    申请号：US14530837

    申请日：2014-11-03

    Applicant: MEDIATEK INC.

    Inventor： Ming-Hsien Lee ,  Yun-Ching Li ,  Yi-Chih Huang ,  Chun-Fang Peng

    IPC: G11C8/18 ,  G11C8/08 ,  G11C8/06 ,  G06F12/02 ,  G11C5/14

    CPC classification number: G11C8/18 ,  G06F12/0607 ,  G06F13/1684 ,  G06F13/1689 ,  G11C5/14 ,  G11C7/1072 ,  G11C8/06 ,  G11C8/08 ,  Y02D10/13 ,  Y02D10/14

    Abstract: A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.

    Abstract translation: 多通道存储器系统具有存储器件，多个通道和控制电路。 存储装置具有多个存储器存储空间。 通道分别耦合到存储器存储空间，其中每个通道被配置为用作独立地访问对应的存储器存储空间的存储器接口。 控制电路分别控制通道上时钟的时钟频率。 在同一时间点，信道至少包括以由控制电路设置的第一时钟频率操作的第一信道和在同一时间点由控制电路设置的第二时钟频率操作的第二信道，以及第二时钟 频率与第一个时钟频率不同。

    Adaptive Thermal Slope Control
    9.
    发明申请
    Adaptive Thermal Slope Control 审中-公开
    自适应热斜率控制

    公开(公告)号：US20170068261A1

    公开(公告)日：2017-03-09

    申请号：US15257022

    申请日：2016-09-06

    Applicant: MEDIATEK INC.

    Inventor： Jih-Ming Hsu ,  Wei-Ting Wang ,  Tai-Yu Chen ,  Wen-Tsan Hsieh ,  Hong-Jie Huang ,  Pei-Yu Huang ,  Ming-Hsien Lee

    IPC: G05D23/19 ,  G05B13/04

    CPC classification number: G05D23/1917 ,  G06F1/206

    Abstract: Methods and apparatus are provided for adaptive thermal slope control for dynamic thermal management. In one novel aspect, the device monitors and obtains sampling temperatures, calculates a thermal-slope index, determines whether the calculated thermal-slope index is greater than a predefined slope threshold, adjusts a power budget based on a thermal-slope algorithm, and applies the dynamic thermal management (DTM) adaptively based on the adjusted power budget. In one embodiment, fixed slope algorithm is used. The power budget is adjusted such that an adjusted slope of temperatures stays at a constant. In another embodiment, the time prediction algorithm is used. The power budget is adjusted such that a predicted time to reach a predefined thermal threshold stays a constant. In one embodiment, the time-prediction algorithm is a time-to-target-point (T2TP) algorithm. The T2TP is obtained using a linear equation or a LOG equation.

    Abstract translation: 提供了用于动态热管理的自适应热边坡控制的方法和装置。 在一个新颖的方面，设备监测和获取采样温度，计算热斜率指数，确定计算的热斜率指数是否大于预定义的斜率阈值，基于热斜率算法调整功率预算，并应用 基于调整后的功率预算自动进行动态热管理（DTM）。 在一个实施例中，使用固定斜率算法。 调整功率预算，使得调整的温度斜率保持恒定。 在另一个实施例中，使用时间预测算法。 调整功率预算，使得达到预定义热阈值的预测时间保持不变。 在一个实施例中，时间预测算法是时间到目标点（T2TP）算法。 使用线性方程或LOG方程获得T2TP。

    CRITICAL PATH EMULATING APPARATUS USING HYBRID ARCHITECTURE
    10.
    发明申请
    CRITICAL PATH EMULATING APPARATUS USING HYBRID ARCHITECTURE 审中-公开
    使用混合建筑的关键路径仿真设备

    公开(公告)号：US20140136177A1

    公开(公告)日：2014-05-15

    申请号：US13672723

    申请日：2012-11-09

    Applicant: MEDIATEK INC.

    Inventor： Ming-Hsien Lee ,  Shih-Tsung Hsiao ,  Hsin-Chen Chen

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F2217/78

    Abstract: A critical path emulating apparatus includes a critical path emulator (CPE) and an interconnection circuit. The CPE is capable of emulating a critical path of a target device, and supporting a plurality of speed information detection modes. The interconnection circuit is capable of supporting a plurality of interconnection arrangements, wherein when the interconnection circuit is configured to have a first interconnection arrangement, the CPE is capable of being used in a first speed information detection mode, and when the interconnection circuit is configured to have a second interconnection arrangement, the CPE is capable of being used in a second speed information detection mode.

    Abstract translation: 关键路径仿真装置包括关键路径仿真器（CPE）和互连电路。 CPE能够模拟目标设备的关键路径，并支持多种速度信息检测模式。 互连电路能够支持多个互连布置，其中当互连电路被配置为具有第一互连布置时，CPE能够用于第一速度信息检测模式，并且当互连电路被配置为 具有第二互连布置，CPE能够用于第二速度信息检测模式。

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