公开(公告)号：US20230396250A1

公开(公告)日：2023-12-07

申请号：US18204374

申请日：2023-05-31

Applicant: MEDIATEK INC.

Inventor： Chen-Han Tsai ,  Chia-Hao Hsu ,  Zhi-Gang Zeng ,  Cheng-Tang Chen

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0944

CPC classification number: H03K19/0016 ,  H03K19/018514 ,  H03K19/0944

Abstract: The present invention provides a clock buffer, wherein the clock buffer receives an input signal at a first node and generate an output signal at a second node. The clock buffer includes a P-type transistor, a first N-type transistor, a resistor, a transistor and a switch. A source electrode, a gate electrode and a drain electrode of the P-type transistor are coupled to a supply voltage, the first node, and the second node, respectively. A gate electrode, a drain electrode and a source electrode of the first N-type transistor are coupled to the first node, the second node and a third node, respectively. The resistor is coupled between the first node and the second node. The transistor is coupled between the first N-type transistor and a ground voltage. The switch is configured to selectively connect the third node to the ground voltage.