公开(公告)号：US20240370579A1

公开(公告)日：2024-11-07

申请号：US18142968

申请日：2023-05-03

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan Finkelshtein ,  Michael Tahar ,  Irit Granovsky ,  Yaniv Strassberg ,  Guy-Avraham Harel

IPC: G06F21/60 ,  G06F21/62

Abstract: A system, circuit, and method are described, among other things. An illustrative system is disclosed to include a processor and a memory storing data for processing by the processor. The data, when processed, causes the processor to receive an initiator message comprising a request to access one or more registers of a plurality of registers, determine that the initiator message corresponds to an entry of a privilege access table, determine a configured level of access control for the initiator message to access the one or more requested registers based at least in part on a group mapping table, and provide a level of access to the one or more requested registers corresponding to the received initiator message based on the initiator message corresponding to the entry of the privilege access table and based, at least in part, on the determined configured level of access control.

公开(公告)号：US20190243936A1

公开(公告)日：2019-08-08

申请号：US15891395

申请日：2018-02-08

Applicant: Mellanox Technologies, Ltd.

Inventor： Moshe Noah ,  Itamar Rabenstein ,  Irit Granovsky

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/505

Abstract: A method for circuit design automation includes appending a non-synthesizable input having a unique identifier to HDL code that specifies a physical input of the circuit. For the physical components in the circuit to which a signal from the physical input is to propagate, corresponding non-synthesizable components are appended, having respective identifiers assigned responsively to the unique identifier of the non-synthesizable input, to the HDL code that specifies the physical components. The design is verified by simulating operation of the circuit using the HDL code, including both the physical and non-synthesizable inputs and components. After verifying the design, a netlist synthesis tool automatically generates a netlist of the circuit including the physical inputs and components while omitting the non-synthesizable inputs and components.