公开(公告)号：US20190384867A1

公开(公告)日：2019-12-19

申请号：US16010536

申请日：2018-06-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Or Davidi ,  Roy Armoni

IPC: G06F17/50

Abstract: An apparatus for IC design includes a memory configured to store an original Register Transfer Level (RTL) model, a corrected RTL model, and a translation of the original RTL model into a netlist. A processor is configured to identify in the original RTL model a flip-flop having a next-state function that is not equivalent to a corresponding next-state function of a corresponding flip-flop in the Corrected RTL model, to find a wire, which is the earliest ancestor of the flip-flop for which there is no equivalence between the original RTL model and the corrected RTL model, to check whether the wire has an equivalent net in the netlist, to identify, upon finding that the wire has no equivalent net, one or more ancestors of the wire, which do have equivalent nets in the netlist, and to modify the netlist to match the corrected RTL model.

公开(公告)号：US10140405B2

公开(公告)日：2018-11-27

申请号：US15387958

申请日：2016-12-22

Applicant: Mellanox Technologies, Ltd.

Inventor： Roy Armoni ,  Or Davidi

IPC: G06F17/50

Abstract: A method, computer program, and apparatus are described for finding the logical equivalence between register transfer level (RTL) wires and post synthesis nets in a netlist. In some example embodiments, the method includes minimizing nets in a netlist and matching each RTL wire to a netlist net. In some example embodiments, the method also includes determining if an RTL wire is logically equivalent to a netlist net. In some example embodiments, the method also includes determining a new candidate for a net if the RTL wire and associated netlist net are not logically equivalent.

公开(公告)号：US10599802B2

公开(公告)日：2020-03-24

申请号：US16010536

申请日：2018-06-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Or Davidi ,  Roy Armoni

IPC: G06F17/50

Abstract: An apparatus for IC design includes a memory configured to store an original Register Transfer Level (RTL) model, a corrected RTL model, and a translation of the original RTL model into a netlist. A processor is configured to identify in the original RTL model a flip-flop having a next-state function that is not equivalent to a corresponding next-state function of a corresponding flip-flop in the Corrected RTL model, to find a wire, which is the earliest ancestor of the flip-flop for which there is no equivalence between the original RTL model and the corrected RTL model, to check whether the wire has an equivalent net in the netlist, to identify, upon finding that the wire has no equivalent net, one or more ancestors of the wire, which do have equivalent nets in the netlist, and to modify the netlist to match the corrected RTL model.

公开(公告)号：US10460060B2

公开(公告)日：2019-10-29

申请号：US15822241

申请日：2017-11-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Or Davidi ,  Roy Armoni

IPC: G06F17/50

Abstract: A method for circuit design automation includes receiving an initial RTL definition of a design of a circuit, and synthesizing an initial netlist of the circuit based on the initial RTL definition. After synthesizing the initial netlist, an updated RTL definition containing a design change and a corresponding updated netlist are received. The updated RTL definition and netlist are automatically analyzed to identify first and second logical relations that were changed in the RTL definition and netlist, respectively. A notification is issued of sets of the endpoints between which the first logical relations were changed without changes to the second logical relations or vice versa. For the sets of the endpoints between which both the first logical relations and the second logical relations were changed, the equivalence between the first and second logical relations is automatically verified.

公开(公告)号：US20190163844A1

公开(公告)日：2019-05-30

申请号：US15822241

申请日：2017-11-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Or Davidi ,  Roy Armoni

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/504

Abstract: A method for circuit design automation includes receiving an initial RTL definition of a design of a circuit, and synthesizing an initial netlist of the circuit based on the initial RTL definition. After synthesizing the initial netlist, an updated RTL definition containing a design change and a corresponding updated netlist are received. The updated RTL definition and netlist are automatically analyzed to identify first and second logical relations that were changed in the RTL definition and netlist, respectively. A notification is issued of sets of the endpoints between which the first logical relations were changed without changes to the second logical relations or vice versa. For the sets of the endpoints between which both the first logical relations and the second logical relations were changed, the equivalence between the first and second logical relations is automatically verified.