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    Digital period divider
    1.
    发明授权
    Digital period divider 有权
    数字周期分频器

    公开(公告)号：US08908823B2

    公开(公告)日：2014-12-09

    申请号：US14200317

    申请日：2014-03-07

    Applicant: Microchip Technology Incorporated

    Inventor： Joseph Julicher ,  Kevin Kilzer ,  Cobus Van Eeden

    IPC: G01P3/00 ,  H03K23/00

    CPC classification number: H03K23/00 ,  G01P3/481 ,  G01P3/486 ,  G01P3/487 ,  G01P3/488 ,  G01P3/489 ,  H02P6/17 ,  H03K21/38 ,  H03K23/40

    Abstract: A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter.

    Abstract translation: 数字周期分配器具有具有R个最低有效位（LSB）和P个最高有效位（MSB）的第一计数器，其具有计数输入和复位输入，其中所述计数输入接收第一时钟信号，并且所述复位输入接收第二时钟 信号; 具有P位并与第一计数器的P位耦合的锁存器; 具有P位和计数输入和复位输入的第二计数器，其中所述计数输入接收所述第一时钟信号; 以及第一比较器，用于将锁存器的P位与第二计数器的P位进行比较并产生输出信号，其中输出信号也被馈送到第二计数器的复位输入。

    DIGITAL PERIOD DIVIDER
    2.
    发明申请
    DIGITAL PERIOD DIVIDER 审中-公开
    数字分时器

    公开(公告)号：US20150219474A1

    公开(公告)日：2015-08-06

    申请号：US14608753

    申请日：2015-01-29

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Joseph Julicher ,  Kevin Kilzer ,  Cobus Van Eeden

    IPC: G01D5/14 ,  G01D5/26

    CPC classification number: G01D5/142 ,  G01D5/2451 ,  G01D5/26 ,  G01P3/481 ,  G01P3/486 ,  G01P3/488 ,  G01P3/489 ,  H02P6/16 ,  H02P23/22 ,  H03K21/38

    Abstract: A system may have a digital period divider generating an output signal that is proportional to an angle defined by a rotational input signal and an interval measurement unit determining an interval time of an interval defined by succeeding pulses of the input output signal. In an enhancement, the system may also have a missing pulse detector which is operable to compare a current interval with a parameter to determine whether a pulse is missing in the input signal.

    Abstract translation: 系统可以具有产生与由旋转输入信号限定的角度成比例的输出信号的数字周期分配器和间隔测量单元，其确定由输入输出信号的后续脉冲定义的间隔的间隔时间。 在增强中，系统还可以具有丢失的脉冲检测器，其可操作以将当前间隔与参数进行比较，以确定输入信号中脉冲是否丢失。

    Digital Period Divider
    4.
    发明申请
    Digital Period Divider 有权
    数字时钟分频器

    公开(公告)号：US20140270048A1

    公开(公告)日：2014-09-18

    申请号：US14200317

    申请日：2014-03-07

    Applicant: Microchip Technology Incorporated

    Inventor： Joseph Julicher ,  Kevin Kilzer ,  Cobus Van Eeden

    IPC: H03K23/00

    CPC classification number: H03K23/00 ,  G01P3/481 ,  G01P3/486 ,  G01P3/487 ,  G01P3/488 ,  G01P3/489 ,  H02P6/17 ,  H03K21/38 ,  H03K23/40

    Abstract: A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter.

    Abstract translation: 数字周期分配器具有具有R个最低有效位（LSB）和P个最高有效位（MSB）的第一计数器，其具有计数输入和复位输入，其中所述计数输入接收第一时钟信号，并且所述复位输入接收第二时钟 信号; 具有P位并与第一计数器的P位耦合的锁存器; 具有P位和计数输入和复位输入的第二计数器，其中所述计数输入接收所述第一时钟信号; 以及第一比较器，用于将锁存器的P位与第二计数器的P位进行比较并产生输出信号，其中输出信号也被馈送到第二计数器的复位输入。

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