公开(公告)号：US20130254476A1

公开(公告)日：2013-09-26

申请号：US13830377

申请日：2013-03-14

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Zeke Lundstrum ,  Fanie Duvenhage ,  Sean Steedman ,  Kevin Lee Kilzer ,  Joseph Julicher

IPC: G06F9/48

CPC classification number: G06F9/4812 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30138

Abstract: A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

Abstract translation: 微处理器或微控制器设备可以具有中央处理单元（CPU），与CPU耦合的数据存储器，其中数据存储器被分成多个存储体，其中存储体选择寄存器确定当前与 中央处理器。 此外，提供第一和第二组特殊功能寄存器，其中在上下文切换发生时，第一组或第二组特殊功能寄存器被选择为用于CPU和相应的另一组特殊功能寄存器的活动上下文寄存器 被选择为非活动上下文寄存器，其中活动上下文寄存器的至少一些寄存器被存储器映射到数据存储器的多于两个存储体，并且其中非活动上下文寄存器的所有寄存器被存储器映射到至少一个存储器位置 在数据存储器内。

公开(公告)号：US09195497B2

公开(公告)日：2015-11-24

申请号：US13830377

申请日：2013-03-14

Applicant: Microchip Technology Incorporated

Inventor： Zeke Lundstrum ,  Fanie Duvenhage ,  Sean Steedman ,  Kevin Lee Kilzer ,  Joseph Julicher

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4812 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30138

Abstract: A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

Abstract translation: 微处理器或微控制器设备可以具有中央处理单元（CPU），与CPU耦合的数据存储器，其中数据存储器被分成多个存储体，其中存储体选择寄存器确定当前与 中央处理器。 此外，提供第一和第二组特殊功能寄存器，其中在上下文切换发生时，第一组或第二组特殊功能寄存器被选择为用于CPU和相应的另一组特殊功能寄存器的活动上下文寄存器 被选择为非活动上下文寄存器，其中活动上下文寄存器的至少一些寄存器被存储器映射到数据存储器的多于两个存储体，并且其中非活动上下文寄存器的所有寄存器被存储器映射到至少一个存储器位置 在数据存储器内。