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    APPARATUSES AND METHODS FOR SELECTIVE ROW REFRESHES
    1.
    发明申请
    APPARATUSES AND METHODS FOR SELECTIVE ROW REFRESHES 审中-公开
    选择性刷新的方法和方法

    公开(公告)号：US20150243339A1

    公开(公告)日：2015-08-27

    申请号：US14707893

    申请日：2015-05-08

    Applicant: Micron Technology, Inc.

    Inventor： DEBRA M. BELL ,  Jeff A. McClain ,  Brian P. Callaway

    IPC: G11C11/406

    CPC classification number: G11C11/406 ,  G11C7/1012

    Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

    Abstract translation: 本文公开了用于选择行刷新的装置和方法。 示例性装置可以包括刷新控制电路。 刷新控制电路可以被配置为从地址总线接收与目标多个存储器单元相关联的目标地址。 刷新控制电路还可以被配置为至少部分地响应于确定已经发生了多个刷新操作来向地址总线提供邻近地址。 在一些示例中，与邻近地址相关联的多个存储单元可以是与目标多个存储单元相邻的多个存储单元。

    APPARATUSES AND METHODS FOR SELECTIVE ROW REFRESHES
    3.
    发明申请
    APPARATUSES AND METHODS FOR SELECTIVE ROW REFRESHES 审中-公开

    公开(公告)号：US20190051344A1

    公开(公告)日：2019-02-14

    申请号：US16160801

    申请日：2018-10-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： DEBRA M. BELL ,  Jeff A. McClain ,  Brian P. Callaway

    IPC: G11C11/406 ,  G11C7/10

    Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

    APPARATUSES AND METHODS FOR INFERENCE PROCESSING ON EDGE DEVICES
    5.
    发明申请
    APPARATUSES AND METHODS FOR INFERENCE PROCESSING ON EDGE DEVICES 有权

    公开(公告)号：US20210326732A1

    公开(公告)日：2021-10-21

    申请号：US16849819

    申请日：2020-04-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： DEBRA M. BELL ,  JAMES S. REHMEYER ,  BRETT K. DODDS ,  ANTHONY D. VECHES ,  LIBO WANG ,  DI WU

    IPC: G06N5/04 ,  G06N20/00 ,  H04L29/08

    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods for an internet of things (IoT) system to include edge devices that perform at least some functions without communicating with a cloud computing system. An edge device may include a memory with on-memory pattern matching capabilities. The edge device may perform pattern matching operations on data collected by the edge device or sensors in communication with the edge device. Based on results of the pattern matching operations, the edge device may perform various functions, such as transmitting data to the cloud computing system, activating an alarm, and/or changing a frequency at which data is transmitted.

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