公开(公告)号：US20150243339A1

公开(公告)日：2015-08-27

申请号：US14707893

申请日：2015-05-08

Applicant: Micron Technology, Inc.

Inventor： DEBRA M. BELL ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C7/1012

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract translation: 本文公开了用于选择行刷新的装置和方法。 示例性装置可以包括刷新控制电路。 刷新控制电路可以被配置为从地址总线接收与目标多个存储器单元相关联的目标地址。 刷新控制电路还可以被配置为至少部分地响应于确定已经发生了多个刷新操作来向地址总线提供邻近地址。 在一些示例中，与邻近地址相关联的多个存储单元可以是与目标多个存储单元相邻的多个存储单元。

公开(公告)号：US20190051344A1

公开(公告)日：2019-02-14

申请号：US16160801

申请日：2018-10-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： DEBRA M. BELL ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

公开(公告)号：US10134461B2

公开(公告)日：2018-11-20

申请号：US14707893

申请日：2015-05-08

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

公开(公告)号：US11264075B2

公开(公告)日：2022-03-01

申请号：US16160801

申请日：2018-10-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

公开(公告)号：US09047978B2

公开(公告)日：2015-06-02

申请号：US14010120

申请日：2013-08-26

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

CPC classification number: G11C11/406 ,  G11C7/1012

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract translation: 本文公开了用于选择行刷新的装置和方法。 示例性装置可以包括刷新控制电路。 刷新控制电路可以被配置为从地址总线接收与目标多个存储器单元相关联的目标地址。 刷新控制电路还可以被配置为至少部分地响应于确定已经发生了多个刷新操作来向地址总线提供邻近地址。 在一些示例中，与邻近地址相关联的多个存储单元可以是与目标多个存储单元相邻的多个存储单元。

公开(公告)号：US20150055420A1

公开(公告)日：2015-02-26

申请号：US14010120

申请日：2013-08-26

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

CPC classification number: G11C11/406 ,  G11C7/1012

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

公开(公告)号：US11361808B2

公开(公告)日：2022-06-14

申请号：US16160801

申请日：2018-10-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

公开(公告)号：US10930335B2

公开(公告)日：2021-02-23

申请号：US16231327

申请日：2018-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

公开(公告)号：US20190130961A1

公开(公告)日：2019-05-02

申请号：US16231327

申请日：2018-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may he configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.