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公开(公告)号：US20210055979A1
公开(公告)日：2021-02-25
申请号：US17092778
申请日：2020-11-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Suresh Rajgopal , Dan E. Soto , Steven Eskildsen
Abstract: Apparatus having a plurality of sets of memory devices and a multiplexer, wherein each set of memory devices of the plurality of sets of memory devices corresponds to a respective enable signal of a plurality of enable signals, wherein, for each set of memory devices of the plurality of sets of memory devices, each memory device of that set of memory devices is configured to receive commands in response to the respective enable signal for that set of memory devices having a particular logic level, and wherein, for each set of memory devices of the plurality of sets of memory devices, the multiplexer is configured to selectively connect input/output signal lines of that set of memory devices to an interface of the apparatus in response to the respective enable signal for that set of memory devices.
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公开(公告)号：US11385949B2
公开(公告)日：2022-07-12
申请号：US17092778
申请日：2020-11-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Suresh Rajgopal , Dan E. Soto , Steven Eskildsen
Abstract: Apparatus having a plurality of sets of memory devices and a multiplexer, wherein each set of memory devices of the plurality of sets of memory devices corresponds to a respective enable signal of a plurality of enable signals, wherein, for each set of memory devices of the plurality of sets of memory devices, each memory device of that set of memory devices is configured to receive commands in response to the respective enable signal for that set of memory devices having a particular logic level, and wherein, for each set of memory devices of the plurality of sets of memory devices, the multiplexer is configured to selectively connect input/output signal lines of that set of memory devices to an interface of the apparatus in response to the respective enable signal for that set of memory devices.
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