公开(公告)号：US20210055979A1

公开(公告)日：2021-02-25

申请号：US17092778

申请日：2020-11-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Suresh Rajgopal ,  Dan E. Soto ,  Steven Eskildsen

IPC: G06F11/07 ,  G06F12/02 ,  G06F13/10

Abstract: Apparatus having a plurality of sets of memory devices and a multiplexer, wherein each set of memory devices of the plurality of sets of memory devices corresponds to a respective enable signal of a plurality of enable signals, wherein, for each set of memory devices of the plurality of sets of memory devices, each memory device of that set of memory devices is configured to receive commands in response to the respective enable signal for that set of memory devices having a particular logic level, and wherein, for each set of memory devices of the plurality of sets of memory devices, the multiplexer is configured to selectively connect input/output signal lines of that set of memory devices to an interface of the apparatus in response to the respective enable signal for that set of memory devices.

公开(公告)号：US20190354301A1

公开(公告)日：2019-11-21

申请号：US15982978

申请日：2018-05-17

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Henrico L. Yahja ,  Steven Eskildsen ,  Dustin J. Carter

IPC: G06F3/06

Abstract: A selection device can be operatively coupled with non-volatile memory devices. Enable signals that are based on an architecture of non-volatile memory devices can be received. Data can be transmitted to the non-volatile memory devices based on the enable signals that are based on the architecture of the non-volatile memory devices.

公开(公告)号：US08829693B2

公开(公告)日：2014-09-09

申请号：US14027515

申请日：2013-09-16

Applicant: Micron Technology, Inc.

Inventor： Mostafa Naguib Abdulla ,  Steven Eskildsen

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L23/49816 ,  H01L21/44 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects.

Abstract translation: 本文公开的实施例可以涉及用于集成电路器件的电源电压或接地连接。 作为一个示例，两个或更多个电源电压键合指可以经由一个或多个导电互连件连接在一起。

公开(公告)号：US08860496B2

公开(公告)日：2014-10-14

申请号：US14021268

申请日：2013-09-09

Applicant: Micron Technology, Inc.

Inventor： Mostafa Naguib Abdulla ,  Steven Eskildsen

IPC: G11C5/14 ,  H01L23/50 ,  H01L27/02 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L27/0214 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399

Abstract: Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond pads on an integrated circuit die may be connected together via one or more electrically conductive interconnects.

Abstract translation: 本文公开的实施例可以涉及用于集成电路器件的电源电压或接地连接。 作为一个示例，集成电路管芯上的两个或更多个电源电压接合焊盘可以经由一个或多个导电互连件连接在一起。

公开(公告)号：US11385949B2

公开(公告)日：2022-07-12

申请号：US17092778

申请日：2020-11-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Suresh Rajgopal ,  Dan E. Soto ,  Steven Eskildsen

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/02 ,  G06F13/10

Abstract: Apparatus having a plurality of sets of memory devices and a multiplexer, wherein each set of memory devices of the plurality of sets of memory devices corresponds to a respective enable signal of a plurality of enable signals, wherein, for each set of memory devices of the plurality of sets of memory devices, each memory device of that set of memory devices is configured to receive commands in response to the respective enable signal for that set of memory devices having a particular logic level, and wherein, for each set of memory devices of the plurality of sets of memory devices, the multiplexer is configured to selectively connect input/output signal lines of that set of memory devices to an interface of the apparatus in response to the respective enable signal for that set of memory devices.

公开(公告)号：US10366934B2

公开(公告)日：2019-07-30

申请号：US16196262

申请日：2018-11-20

Applicant: Micron Technology, Inc.

Inventor： Chan Yoo ,  Akshay Singh ,  Yi Xu ,  Liana Foster ,  Steven Eskildsen

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48

Abstract: A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.

公开(公告)号：US10153221B1

公开(公告)日：2018-12-11

申请号：US15621102

申请日：2017-06-13

Applicant: Micron Technology, Inc.

Inventor： Chan Yoo ,  Akshay Singh ,  Yi Xu ,  Liana Foster ,  Steven Eskildsen

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657

Abstract: A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.

公开(公告)号：US20140015133A1

公开(公告)日：2014-01-16

申请号：US14027515

申请日：2013-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mostafa Naguib Abdulla ,  Steven Eskildsen

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L21/44 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects.

Abstract translation: 本文公开的实施例可以涉及用于集成电路器件的电源电压或接地连接。 作为一个示例，两个或更多个电源电压键合指可以经由一个或多个导电互连件连接在一起。

公开(公告)号：US11347415B2

公开(公告)日：2022-05-31

申请号：US17135476

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Henrico L. Yahja ,  Steven Eskildsen ,  Dustin J. Carter

IPC: G06F3/06

Abstract: A selection device includes a multiplexer component, an input channel configured to couple at least the multiplexer to the memory sub-system controller, and a set of output channels coupled to the multiplexer component. Each of the set of output channels is further coupled to a respective memory device of a set of memory devices. Each of the set of output channels is configured to transmit data between the multiplexer component and the respective memory device. The selection device further includes a decoder component that is coupled to the input channel and each of the set of memory devices. The decoder component is configured to receive, from the memory sub-system controller via the input channel, a signal including a first signal portion configured to enable the decoder component and a second signal portion configured to identify a particular output channel of the set of output channels that is to transmit the data between the multiplexer component and the corresponding memory device. The decoder component is to decode the received signal and transmit the decoded signal to each of the set of memory devices. The decoded signal is to enable the transmission of the data between the multiplexer and the corresponding memory device via the particular output channel.

公开(公告)号：US20180358275A1

公开(公告)日：2018-12-13

申请号：US15621102

申请日：2017-06-13

Applicant: Micron Technology, Inc.

Inventor： Chan Yoo ,  Akshay Singh ,  Yi Xu ,  Liana Foster ,  Steven Eskildsen

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657

Abstract: A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.