公开(公告)号：US20200302994A1

公开(公告)日：2020-09-24

申请号：US16358587

申请日：2019-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Masaru Morohashi

IPC: G11C11/406 ,  G11C11/408 ,  G06F7/58

Abstract: Disclosed herein is an apparatus that includes a plurality of address registers each storing an address signal, a plurality of counter circuits each storing a count value corresponding to an associated one of the address registers, a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

公开(公告)号：US11521669B2

公开(公告)日：2022-12-06

申请号：US17301533

申请日：2021-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Masaru Morohashi

IPC: G11C11/406 ,  G06F7/58 ,  G11C11/408

Abstract: An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

公开(公告)号：US11222682B1

公开(公告)日：2022-01-11

申请号：US17007069

申请日：2020-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Masaru Morohashi

IPC: G11C11/406

Abstract: Apparatuses and methods for generating refresh addresses for row hammer refresh operations are disclosed. In some examples, determination of a row address associated with a highest count value may be initiated at a precharge command preceding a row hammer refresh operation. The row address determined to be associated with the highest count value may be provided for generating the refresh addresses.

公开(公告)号：US20210225432A1

公开(公告)日：2021-07-22

申请号：US17301533

申请日：2021-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Masaru Morohashi

IPC: G11C11/406 ,  G06F7/58 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a plurality of address registers each storing an address signal, a plurality of counter circuits each storing a count value corresponding to an associated one of the address registers, a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

公开(公告)号：US20250140303A1

公开(公告)日：2025-05-01

申请号：US18751894

申请日：2024-06-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Takashi Tomatsu ,  Masaru Morohashi ,  Hideo Shimizu

IPC: G11C11/4076 ,  G11C11/4096

Abstract: An example apparatus includes a first circuit configured to activate a first control signal, a second circuit configured to activate a first timing signal after receiving the first control signal, a third circuit configured to receive the first timing signal from the second control circuit and return back the first timing signal to the second control circuit, a first signal line conveying the first control signal from the first circuit to the second circuit, a second signal line conveying the first timing signal from the second circuit to the third circuit, and a third signal line conveying the first timing signal from the third circuit to the second circuit. Each of the first to third signal lines is provided on first and second tracks extending in parallel with each other.

公开(公告)号：US11043254B2

公开(公告)日：2021-06-22

申请号：US16358587

申请日：2019-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Masaru Morohashi

IPC: G11C11/408 ,  G11C11/406 ,  G06F7/58

Abstract: An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.