公开(公告)号：US20230223059A1

公开(公告)日：2023-07-13

申请号：US17575378

申请日：2022-01-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Hiroshi Akamatsu ,  Jian Long ,  Kevin G. Werhane ,  Liang Liu ,  Yoshinori Fujiwara

IPC: G11C7/10

CPC classification number: G11C7/1087

Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.

公开(公告)号：US11727967B2

公开(公告)日：2023-08-15

申请号：US17575378

申请日：2022-01-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Hiroshi Akamatsu ,  Jian Long ,  Kevin G. Werhane ,  Liang Liu ,  Yoshinori Fujiwara

IPC: G11C7/10

CPC classification number: G11C7/1087

Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.

公开(公告)号：US20230343376A1

公开(公告)日：2023-10-26

申请号：US18335385

申请日：2023-06-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Hiroshi Akamatsu ,  Jian Long ,  Kevin G. Werhane ,  Liang Liu ,  Yoshinori Fujiwara

IPC: G11C7/10

CPC classification number: G11C7/1087

Abstract: According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.