公开(公告)号：US20210166753A1

公开(公告)日：2021-06-03

申请号：US17173048

申请日：2021-02-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Yoshinori Matsui ,  Kiyohiro Furutani ,  Takahiko Fukiage ,  Ki-Jun Nam ,  John D. Porter

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times When the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

公开(公告)号：US10020045B2

公开(公告)日：2018-07-10

申请号：US14285279

申请日：2014-05-22

Applicant: Micron Technology, Inc.

Inventor： Yoshiro Riho

IPC: G11C11/406 ,  G11C5/14

CPC classification number: G11C11/40615 ,  G11C11/40622

Abstract: Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required. One bit data may be stored into 1 cell for a normal operation mode and stored into 2N cells for a self refresh operation mode for a first partial access mode, while one bit data may be stored into 2N cells for both normal and self refresh operation modes.

公开(公告)号：US11314591B2

公开(公告)日：2022-04-26

申请号：US17017254

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Yoshiro Riho ,  Atsushi Shimizu ,  Sang-Kyun Park ,  Jongtae Kwak

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  H03M13/00 ,  G11C29/04 ,  G06F13/42

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.

公开(公告)号：US20210357137A1

公开(公告)日：2021-11-18

申请号：US17392085

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

IPC: G06F3/06 ,  G11C7/10 ,  G06F13/16

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

公开(公告)号：US20240170091A1

公开(公告)日：2024-05-23

申请号：US18511440

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Yoshiro Riho ,  Hyun Yoo Lee ,  Yang Lu

IPC: G11C29/52 ,  G11C7/08 ,  G11C7/10

CPC classification number: G11C29/52 ,  G11C7/08 ,  G11C7/1039

Abstract: Described apparatuses and methods provide system error correction code (ECC) circuitry routing that segregates even sense amp (SA) line data sets and odd SA line data sets in a memory, such as a low-power dynamic random-access memory. A memory device may include one or more dies, and a die can have even SA line data sets and odd SA line data sets. The memory device may also include ECC circuitry comprising one or more ECC engines. By segregating the data sets, instead of coupling even and odd SA line data sets to a single ECC engine, double-bit errors on a single word line may be separated into two single-bit errors. Thus, by utilizing system ECC circuitry routing in this way, even a one-bit ECC algorithm may be used to correct double bits, which may increase data reliability.

公开(公告)号：US20230223059A1

公开(公告)日：2023-07-13

申请号：US17575378

申请日：2022-01-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Hiroshi Akamatsu ,  Jian Long ,  Kevin G. Werhane ,  Liang Liu ,  Yoshinori Fujiwara

IPC: G11C7/10

CPC classification number: G11C7/1087

Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.

公开(公告)号：US10976945B2

公开(公告)日：2021-04-13

申请号：US16048078

申请日：2018-07-27

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F13/16

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

公开(公告)号：US10481819B2

公开(公告)日：2019-11-19

申请号：US15798083

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F13/16

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

公开(公告)号：US20190129635A1

公开(公告)日：2019-05-02

申请号：US15798083

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0673 ,  G06F13/16 ,  G11C7/1045 ,  G11C2207/2272

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

公开(公告)号：US09640240B2

公开(公告)日：2017-05-02

申请号：US14168899

申请日：2014-01-30

Applicant: Micron Technology, Inc.

Inventor： Yoshiro Riho

IPC: G06F12/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40622

Abstract: Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. Although active power increases by a factor of 2N, the refresh time increases by more than 2N as a consequence of the fact that the majority decision does better than averaging for the tail distribution of retention time. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required.