公开(公告)号：US11205479B2

公开(公告)日：2021-12-21

申请号：US15931080

申请日：2020-05-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John Fredric Schreck ,  Hari Giduturi

IPC: G11C13/00

Abstract: An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.

公开(公告)号：US11749342B2

公开(公告)日：2023-09-05

申请号：US17549390

申请日：2021-12-13

Applicant: Micron Technology, Inc.

Inventor： John Fredric Schreck ,  Hari Giduturi

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C13/0028

Abstract: An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.

公开(公告)号：US20220101918A1

公开(公告)日：2022-03-31

申请号：US17549390

申请日：2021-12-13

Applicant: Micron Technology, Inc.

Inventor： John Fredric Schreck ,  Hari Giduturi

IPC: G11C13/00

Abstract: An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.

公开(公告)号：US20210358545A1

公开(公告)日：2021-11-18

申请号：US15931080

申请日：2020-05-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John Fredric Schreck ,  Hari Giduturi

IPC: G11C13/00

Abstract: An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.