公开(公告)号：US20170229165A1

公开(公告)日：2017-08-10

申请号：US15499568

申请日：2017-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KENJI YOSHIDA ,  Hiroki Fujisawa

IPC: G11C11/406 ,  G11C11/4094

CPC classification number: G11C11/40626 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2211/4061

Abstract: Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command: and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle, to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.