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    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES, AND ELECTRONIC SYSTEMS
    1.
    发明公开
    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES, AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：US20240244820A1

    公开(公告)日：2024-07-18

    申请号：US18391522

    申请日：2023-12-20

    申请人： Micron Technology, Inc.

    发明人： Scott E. Sills ,  Si-Woo Lee` ,  Richard E. Fackenthal ,  Hiroki Fujisawa

    IPC分类号： H10B12/00

    CPC分类号： H10B12/30

    摘要： A microelectronic device includes memory array regions of memory cells each including a vertical stack structure comprising conductive structures vertically spaced from one another and horizontally extending through a vertical stack of memory cells. A staircase region is horizontally between two of the memory array regions horizontally neighboring one another and includes a first staircase structure horizontally extending from the vertical stack structure of a first of the two of the memory array regions and a second staircase structure horizontally extending from the vertical stack structure of a second of the two of the memory array regions. Lateral conductive contacts provide a conductive path between the first steps of the first staircase structure and the second steps of the second staircase structure. Related microelectronic devices, memory devices, and electronic systems are also described.

    SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER 有权
    半导体存储器件，包括输出缓冲器

    公开(公告)号：US20150235680A1

    公开(公告)日：2015-08-20

    申请号：US14622520

    申请日：2015-02-13

    申请人： Micron Technology, Inc.

    发明人： Hiromasa Takeda ,  Hiroki Fujisawa

    IPC分类号： G11C7/10

    CPC分类号： G11C11/4093 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/4074 ,  G11C11/4094 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

    摘要： An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

    摘要翻译： 一种装置包括：第一终端，被配置为与设备的外部通信数据;第二终端，被配置为接收第一电源电位;第三终端，被配置为接收低于第一电源电位的第二电源电位;第四终端， 被配置为耦合到校准电阻器的输出缓冲器，包括分别耦合到第一至第三端子的第一至第三节点的输出缓冲器以及分别耦合到第二和第三端子的第四和第五节点的复制电路，以及耦合到 第四个终端。

    Apparatus and methods for refreshing memory cells of a semiconductor device
    9.
    发明授权
    Apparatus and methods for refreshing memory cells of a semiconductor device 有权

    公开(公告)号：US10210922B2

    公开(公告)日：2019-02-19

    申请号：US15962886

    申请日：2018-04-25

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Kenji Yoshida ,  Hiroki Fujisawa

    IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094

    摘要： Apparatuses and methods for refreshing memory cells of a semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

    Apparatuses and methods for refreshing memory cells of a semiconductor device
    10.
    发明授权
    Apparatuses and methods for refreshing memory cells of a semiconductor device 有权

    公开(公告)号：US09984738B2

    公开(公告)日：2018-05-29

    申请号：US15499568

    申请日：2017-04-27

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Kenji Yoshida ,  Hiroki Fujisawa

    IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/4094

    CPC分类号： G11C11/40626 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2211/4061

    摘要： Apparatuses and methods for refreshing memory cells of semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.