公开(公告)号：US11984186B2

公开(公告)日：2024-05-14

申请号：US17454443

申请日：2021-11-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Hulton ,  Tamara Schmitz ,  Jonathan D. Harms ,  Jeremy Chritz ,  Kevin Majerus

IPC: G11C29/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/126 ,  G06F11/10 ,  G06F12/0813 ,  G11C11/408 ,  G11C11/418 ,  G11C29/04 ,  G11C29/44 ,  H04L61/2575

CPC classification number: G11C29/76 ,  G06F3/0659 ,  G06F12/0246 ,  G06F12/126 ,  G06F11/1048 ,  G06F12/0813 ,  G11C11/408 ,  G11C11/418 ,  G11C29/04 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/787 ,  H04L61/2575

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

公开(公告)号：US11183266B2

公开(公告)日：2021-11-23

申请号：US16453905

申请日：2019-06-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Hulton ,  Tamara Schmitz ,  Jonathan D. Harms ,  Jeremy Chritz ,  Kevin Majerus

IPC: G11C29/00 ,  G06F12/126 ,  G06F12/02 ,  G06F3/06 ,  G11C29/04 ,  G06F12/0813 ,  G11C29/44 ,  H04L29/12 ,  G06F11/10 ,  G11C11/408 ,  G11C11/418

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.