公开(公告)号：US20250037754A1

公开(公告)日：2025-01-30

申请号：US18749394

申请日：2024-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsunari Murayama ,  Mamoru Nishizaki ,  Manami Mizukane ,  Hidekazu Noguchi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4094

Abstract: An example apparatus includes first and second memory cell arrays arranged in a first direction; and a plurality of first and second sub word line drivers, a plurality of main word line drivers, and a plurality of level shift circuits each arranged on an intermediate region between the first and second memory cell arrays. The first and second sub word line drivers are arranged in a second direction and along the first and second memory cell array, respectively. The main word line drivers are arranged in the second direction and adjacently along the plurality of second sub word line drivers. The level shift circuits are arranged in the second direction and adjacently along the plurality of first sub word line drivers. The level shift circuits are configured to provide voltage-level-shifted signals to the plurality of main word line drivers, respectively.