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    Sense amplifier drivers, and related devices, systems, and methods
    1.
    发明授权
    Sense amplifier drivers, and related devices, systems, and methods 有权

    公开(公告)号：US11935584B2

    公开(公告)日：2024-03-19

    申请号：US17935825

    申请日：2022-09-27

    Applicant: Micron Technology, Inc.

    Inventor： Mamoru Nishizaki

    IPC: G11C11/4091 ,  H01L23/528 ,  H10B12/00

    CPC classification number: G11C11/4091 ,  H01L23/528 ,  H10B12/50

    Abstract: Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed.

    Sense amplifier drivers, and related devices, systems, and methods
    2.
    发明授权
    Sense amplifier drivers, and related devices, systems, and methods 有权

    公开(公告)号：US11495282B2

    公开(公告)日：2022-11-08

    申请号：US16991290

    申请日：2020-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Mamoru Nishizaki

    IPC: G11C11/4091 ,  H01L27/108 ,  H01L23/528

    Abstract: Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed.

    Apparatuses and methods for controlling wordlines and sense amplifiers
    3.
    发明授权
    Apparatuses and methods for controlling wordlines and sense amplifiers 有权

    公开(公告)号：US10339980B2

    公开(公告)日：2019-07-02

    申请号：US16029046

    申请日：2018-07-06

    Applicant: Micron Technology, Inc.

    Inventor： Mamoru Nishizaki

    IPC: G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C8/10 ,  G11C11/408 ,  G11C11/4097 ,  G11C29/00 ,  G11C29/02 ,  G11C7/12 ,  H01L27/108 ,  G11C29/12

    Abstract: Apparatuses for controlling defective bit lines in a semiconductor device are described. An example apparatus includes: a first region including a plurality of bit lines, a plurality of word lines and a plurality of memory cells, each memory cell is coupled to an associated bit line and an associated word line; a second region including a plurality of sense amplifiers, each sense amplifier includes a sense node and a column selection switch coupled to the sense node; a third region including a plurality of bleeder circuits, and disposed between the first and second regions; and a plurality of column selection lines. Each bit line from the first region to the second region is coupled to the sense node of an associated one of the plurality of sense amplifiers, and each column selection line from the column selection switch is coupled to an associated bleeder circuit.

    SEMICONDUCTOR DEVICE HAVING ROW DECODER CIRCUIT
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING ROW DECODER CIRCUIT 有权

    公开(公告)号：US20250029650A1

    公开(公告)日：2025-01-23

    申请号：US18749446

    申请日：2024-06-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： KEIYA ANDO ,  Mamoru Nishizaki ,  KENJI ASAKI

    IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4091

    Abstract: An example apparatus includes: a plurality of first regions each including second and third regions; a plurality of main word driver circuits each configured to activate an associated one of a plurality of main word lines responsive to a row address signal; and a voltage control circuit configured to supply a first power voltage to the plurality of main word driver circuits in a first operation mode and a second power voltage different from the first power voltage to the plurality of main word driver circuits in a second operation mode. One or ones of the plurality of main word driver circuits is arranged in the second region included in each of the plurality of first regions. The voltage control circuit is divided into multiple circuit portions arranged in two or more third regions in two or more of the plurality of first regions, respectively.

    Multilayered network of power supply lines
    6.
    发明授权
    Multilayered network of power supply lines 有权

    公开(公告)号：US10468090B1

    公开(公告)日：2019-11-05

    申请号：US16127030

    申请日：2018-09-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Mamoru Nishizaki

    IPC: G11C11/40 ,  G11C11/4074 ,  G11C7/06 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/06

    Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first power line extending in a first direction, a second wiring layer including second and third power lines extending in a second direction, a third wiring layer including power electrode patterns arranged in the second direction, and a fourth wiring layer including a fourth power line extending in the second direction. The first and second power lines are connected by a first via electrode. The first and third power lines are connected by a second via electrode. The second power line and each of the power electrode patterns are connected by a third via electrode. The third power line and each of the power electrode patterns are connected by a fourth via electrode. The fourth power line and each of the power electrode patterns are connected by a fifth via electrode.

    SENSE AMPLIFIER DRIVERS, AND RELATED DEVICES, SYSTEMS, AND METHODS
    7.
    发明申请
    SENSE AMPLIFIER DRIVERS, AND RELATED DEVICES, SYSTEMS, AND METHODS 有权

    公开(公告)号：US20230014197A1

    公开(公告)日：2023-01-19

    申请号：US17935825

    申请日：2022-09-27

    Applicant: Micron Technology, Inc.

    Inventor： Mamoru Nishizaki

    IPC: G11C11/4091 ,  H01L27/108 ,  H01L23/528

    Abstract: Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed.

    MULTILAYERED NETWORK OF POWER SUPPLY LINES
    8.
    发明申请
    MULTILAYERED NETWORK OF POWER SUPPLY LINES 审中-公开

    公开(公告)号：US20200082868A1

    公开(公告)日：2020-03-12

    申请号：US16656870

    申请日：2019-10-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Mamoru Nishizaki

    IPC: G11C11/4074 ,  G11C7/06 ,  G11C11/4091 ,  G11C5/14

    Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first power line extending in a first direction, a second wiring layer including second and third power lines extending in a second direction, a third wiring layer including power electrode patterns arranged in the second direction, and a fourth wiring layer including a fourth power line extending in the second direction. The first and second power lines are connected by a first via electrode. The first and third power lines are connected by a second via electrode. The second power line and each of the power electrode patterns are connected by a third via electrode. The third power line and each of the power electrode patterns are connected by a fourth via electrode. The fourth power line and each of the power electrode patterns are connected by a fifth via electrode.

    Power supply wiring in a semiconductor memory device
    10.
    发明授权
    Power supply wiring in a semiconductor memory device 有权

    公开(公告)号：US10304497B2

    公开(公告)日：2019-05-28

    申请号：US15709250

    申请日：2017-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Mamoru Nishizaki

    IPC: G11C5/06 ,  H01L23/528 ,  G11C5/02 ,  G11C7/12 ,  G11C7/10 ,  H01L23/522 ,  G11C7/06

    Abstract: The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.

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