公开(公告)号：US20140157066A1

公开(公告)日：2014-06-05

申请号：US13693899

申请日：2012-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Johnson ,  Justin Wood ,  Gregory S. Hendrix ,  Mark D. Franklin ,  Daniel F. Eichenberger

IPC: G11C29/10

CPC classification number: G11C29/40

Abstract: Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches.

Abstract translation: 描述了使用数据压缩进行记忆测试的设备和方法。 一个示例性设备包括多个锁存测试电路，其中多个锁存测试电路中的每一个耦合到存储器的对应全局数据线。 每个锁存测试电路被配置为接收测试数据，并且被配置为从相应的全局数据线或相应的屏蔽位锁存数据。 多个锁存测试电路中的每一个进一步被配置为至少部分地基于对应的屏蔽位来输出数据。 比较电路耦合到每个锁存测试电路的输出，并且被配置为比较由每个锁存测试电路提供的输出数据，并提供具有指示所有输出数据是否匹配的逻辑值的比较器输出。

公开(公告)号：US09443615B2

公开(公告)日：2016-09-13

申请号：US13693899

申请日：2012-12-04

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson ,  Justin Wood ,  Gregory S. Hendrix ,  Mark D. Franklin ,  Daniel F. Eichenberger

IPC: G11C29/00 ,  G11C29/40

CPC classification number: G11C29/40

Abstract: Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches.

Abstract translation: 描述了使用数据压缩进行记忆测试的设备和方法。 一个示例性设备包括多个锁存测试电路，其中多个锁存测试电路中的每一个耦合到存储器的对应全局数据线。 每个锁存测试电路被配置为接收测试数据，并且被配置为从相应的全局数据线或相应的屏蔽位锁存数据。 多个锁存测试电路中的每一个进一步被配置为至少部分地基于对应的屏蔽位来输出数据。 比较电路耦合到每个锁存测试电路的输出，并且被配置为比较由每个锁存测试电路提供的输出数据，并提供具有指示所有输出数据是否匹配的逻辑值的比较器输出。