公开(公告)号：US20240078173A1

公开(公告)日：2024-03-07

申请号：US18353639

申请日：2023-07-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： OSAMU NAGASHIMA ,  YOSHINORI MATSUI ,  KEUN SOO SONG ,  HIROKI TAKAHASHI ,  SHUNICHI SAITO

IPC: G06F12/02 ,  G06F1/08 ,  G06F1/12 ,  G11C11/4076

CPC classification number: G06F12/023 ,  G06F1/08 ,  G06F1/12 ,  G11C11/4076

Abstract: A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.