公开(公告)号：US20150002196A1

公开(公告)日：2015-01-01

申请号：US14317893

申请日：2014-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HIROKI TAKAHASHI ,  Katsuhiro Kitagawa

IPC: H03L7/197

CPC classification number: H03L7/1972 ,  H03L7/0814

Abstract: Disclosed herein is a device includes a first delay circuit delaying a first clock signal according to a count value to generate a second clock signal, a phase determination circuit comparing a phase of the first clock signal with a phase of the second clock signal to generate a phase determination signal, an up-down counter updating the count value according to the phase determination signal each time an update signal is activated, and an update control circuit generating the update signal at a variable interval.

Abstract translation: 本文公开了一种装置，包括：第一延迟电路，根据计数值延迟第一时钟信号以产生第二时钟信号;相位确定电路，将第一时钟信号的相位与第二时钟信号的相位进行比较，以产生 相位确定信号，每当激活更新信号时根据相位确定信号更新计数值的升降计数器，以及以可变间隔产生更新信号的更新控制电路。

公开(公告)号：US20240078173A1

公开(公告)日：2024-03-07

申请号：US18353639

申请日：2023-07-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： OSAMU NAGASHIMA ,  YOSHINORI MATSUI ,  KEUN SOO SONG ,  HIROKI TAKAHASHI ,  SHUNICHI SAITO

IPC: G06F12/02 ,  G06F1/08 ,  G06F1/12 ,  G11C11/4076

CPC classification number: G06F12/023 ,  G06F1/08 ,  G06F1/12 ,  G11C11/4076

Abstract: A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.

公开(公告)号：US20230186971A1

公开(公告)日：2023-06-15

申请号：US17551095

申请日：2021-12-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HIROKI TAKAHASHI ,  TORU ISHIKAWA

IPC: G11C11/4091 ,  G11C11/406

CPC classification number: G11C11/4091 ,  G11C11/406

Abstract: Apparatuses and methods for 1T and 2T memory cell architectures. A memory array includes a word line which has both 1T and 2T portions. In the 1T portion, each sense amplifier is coupled to one memory cell along the word line. In the 2T portion, sense amplifiers are coupled to more than one memory cell along the word line each. For example, each sense amplifier in the 2T portion may be coupled to two bit lines, each of which intersect a memory cell along the word line. In some embodiments, the 2T portion may store a count value which represents an access count to the word line.