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公开(公告)号：US20240331763A1
公开(公告)日：2024-10-03
申请号：US18591798
申请日：2024-02-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： TAKAMASA SUZUKI , NOBUO YAMAMOTO , IZUMI NAKAI
IPC: G11C11/4096 , G11C11/4074 , G11C11/4091
CPC classification number: G11C11/4096 , G11C11/4074 , G11C11/4091
Abstract: Apparatuses and methods for reducing standby current in memory array access circuits are disclosed. An example apparatus includes a activation voltage supply line and a sense amplifier coupled to the activation voltage supply line. The sense amplifier is configured to be activated by an activation voltage provided on the activation voltage supply line. A read-write circuit is coupled to a pair of local input/output lines and a pair of global input/output lines, and further coupled to the activation voltage supply line. The read-write circuit is configured to drive the pair global input/output lines based on voltages of the pair of local input/output lines when activated for a read operation and further configured to drive the pair of local input/output lines based on voltages of the pair of global input/output lines when activated for a write operation.
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公开(公告)号：US20240331794A1
公开(公告)日：2024-10-03
申请号：US18612284
申请日：2024-03-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： TAKAMASA SUZUKI , YASUSHI MATSUBARA , HARUTAKA MAKABE
CPC classification number: G11C29/44 , G11C29/18 , G11C29/24 , G11C2029/1806
Abstract: Self-test circuits of memory devices disclosed herein may include circuitry that adjusts the correspondence between logical and physical addresses to match pre-repair mapping of memory locations. That is, if a memory device has been repaired by remapping logical addresses to new physical addresses, the circuitry of the test circuit restores the pre-repair mapping of the memory device in some examples. In some examples, an unused global column redundancy data path may be repurposed to provide repair information to the self-test circuit to implement the pre-repair mapping.
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