公开(公告)号：US12224037B2

公开(公告)日：2025-02-11

申请号：US17840461

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： Manami Senoo ,  Hidekazu Noguchi ,  Yoshio Mizukane

IPC: G11C7/10 ,  G11C7/08

Abstract: Apparatuses and methods for controlling access to memory cell matrices are described. An example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. One section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals.

公开(公告)号：US20250103226A1

公开(公告)日：2025-03-27

申请号：US18743869

申请日：2024-06-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshio Mizukane

IPC: G06F3/06

Abstract: Memory devices receive refresh management (RFM) commands and perform a targeted refresh operation responsive to the RFM command. Certain conflicts may occur if the RFM command is received while the memory is performing certain operations. An RFM entry circuit receives the RFM command at a first time and then provides an internal RFM signal at a second time. The second time may be the next time a row activation or refresh is performed after receiving the RFM command. The targeted refresh operation is performed responsive to the internal RFM signal.

公开(公告)号：US12106792B2

公开(公告)日：2024-10-01

申请号：US17829096

申请日：2022-05-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yukimi Morimoto ,  Yoshio Mizukane ,  Hidekazu Noguchi

IPC: G11C7/22 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C7/22

Abstract: Apparatuses, systems, and methods for partial array self refresh masking. A memory bank may be divided into a number of segments, each of which is associated with partial-array self-refresh (PASR) logic which provides a mask signal. The mask signal may be deactivated responsive to an access operation performed on the associated segment. While the mask signal is deactivated, self-refresh operations are performed on the segment. A period of time after deactivating the mask signal, the mask signal may be reactivated.