公开(公告)号：US20250140304A1

公开(公告)日：2025-05-01

申请号：US18774032

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Yukimi Morimoto ,  Takayuki Miyamoto ,  Atsuko Momma

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory device includes a command shifter which includes a latch array with latches coupled in series. After receiving a command the command passes through the latch array and a ready pulse is provided when the command exits the array. The latch array is divided into portions (e.g., rows) with each row receiving its own clock signal from a respective clock circuit. Each clock signal is toggling while the command is within that row of the latch array or about to enter that row. For example, when the command is within N latches of the end of the previous row of the latch array or when a setting and command signal indicates the command is about to initially enter the array in that row.

公开(公告)号：US12106792B2

公开(公告)日：2024-10-01

申请号：US17829096

申请日：2022-05-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yukimi Morimoto ,  Yoshio Mizukane ,  Hidekazu Noguchi

IPC: G11C7/22 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C7/22

Abstract: Apparatuses, systems, and methods for partial array self refresh masking. A memory bank may be divided into a number of segments, each of which is associated with partial-array self-refresh (PASR) logic which provides a mask signal. The mask signal may be deactivated responsive to an access operation performed on the associated segment. While the mask signal is deactivated, self-refresh operations are performed on the segment. A period of time after deactivating the mask signal, the mask signal may be reactivated.