公开(公告)号：US10372453B2

公开(公告)日：2019-08-06

申请号：US15624121

申请日：2017-06-15

申请人： MIPS Tech, LLC

发明人： Andrew David Webber ,  Daniel Ángel Chaver Martínez ,  Enrique Sedano Algarabel

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/00

摘要： A method in an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, the method comprising: identifying that an instruction bundle is to be selected for fetching from the second memory in a predetermined future processor cycle; and initiating a fetch of the identified instruction bundle from the second memory a number of processor cycles prior to the predetermined future processor cycle based upon the predetermined fixed plurality of processor cycles taken to fetch from the second memory.