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公开(公告)号：US20240111687A1
公开(公告)日：2024-04-04
申请号：US17960006
申请日：2022-10-04
申请人： MIPS Tech, LLC
发明人： James Robinson
IPC分类号： G06F12/1027
CPC分类号： G06F12/1027 , G06F2212/681
摘要： In one embodiment, a method includes accessing a virtual address from a request to access a memory of the computing device, where virtual addresses are translated to physical addresses of physical memory in the computing device using an N-level page table, and the lowest level of the page table contains page-table entries specifying the physical address of a frame of physical memory. The method includes searching, using the virtual address, a translation lookaside buffer (TLB) including a plurality of TLB entries, each TLB entry including (1) a tag identifying a virtual address associated with the entry and (2) a page-table entry specifying the physical address of a lower-level page table or of a frame of physical memory associated with the virtual address identified in the tag; and iteratively performing, until the virtual address is translated to a physical address, an address-translation procedure that depends on the cached TLB entries.
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公开(公告)号：US11635963B2
公开(公告)日：2023-04-25
申请号：US17364718
申请日：2021-06-30
申请人： MIPS Tech, LLC
摘要： Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
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公开(公告)号：US10754778B2
公开(公告)日：2020-08-25
申请号：US15488649
申请日：2017-04-17
申请人： MIPS Tech, LLC
发明人： Jason Meredith
IPC分类号： G06F12/0862 , G06F9/38 , G06F12/0891 , G06F9/30 , G06F12/08 , H04L12/851 , H04L12/911 , H04L29/06 , H04L29/08 , G06F12/0897
摘要： Methods and systems for improved control of traffic generated by a processor are described. In an embodiment, when a device generates a pre-fetch request for a piece of data or an instruction from a memory hierarchy, the device includes a pre-fetch identifier in the request. This identifier flags the request as a pre-fetch request rather than a non-pre-fetch request, such as a time-critical request. Based on this identifier, the memory hierarchy can then issue an abort response at times of high traffic which suppresses the pre-fetch traffic, as the pre-fetch traffic is not fulfilled by the memory hierarchy. On receipt of an abort response, the device deletes at least a part of any record of the pre-fetch request and if the data/instruction is later required, a new request is issued at a higher priority than the original pre-fetch request.
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公开(公告)号：US10372453B2
公开(公告)日：2019-08-06
申请号：US15624121
申请日：2017-06-15
申请人： MIPS Tech, LLC
摘要： A method in an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, the method comprising: identifying that an instruction bundle is to be selected for fetching from the second memory in a predetermined future processor cycle; and initiating a fetch of the identified instruction bundle from the second memory a number of processor cycles prior to the predetermined future processor cycle based upon the predetermined fixed plurality of processor cycles taken to fetch from the second memory.
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公开(公告)号：US10318296B2
公开(公告)日：2019-06-11
申请号：US15467073
申请日：2017-03-23
申请人： MIPS Tech, LLC
发明人： Andrew Webber
摘要： A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads with differing hardware resources comprising the steps of receiving a plurality of streams of instructions and determining which hardware threads are able to receive instructions for execution, determining whether a thread determined to be available for executing an instructions has the hardware resources available required by that instructions and executing the instruction in dependence on the result of the determination.
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公开(公告)号：US20190138308A1
公开(公告)日：2019-05-09
申请号：US16131158
申请日：2018-09-14
申请人： MIPS Tech, LLC
摘要： A processor is configured to implement an instruction set architecture for accessing data that includes loading data elements from a memory containing data blocks separated by block boundaries. The instruction set architecture includes a first type of data load instruction for loading an aligned data structure from the memory and a second type of data load instruction for loading an unaligned data structure from the memory. The loading includes fetching a data load instruction of the second type and loading from the memory according to the data load instruction of the second type. The resulting data structure formed of n consecutive data elements is determined from the data load instruction. The data structure loaded from memory is formed of n consecutive unaligned data elements. The processor is similarly configured to implement storing data elements from a set of registers to a memory containing data blocks separated by block boundaries.
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公开(公告)号：US20190065145A1
公开(公告)日：2019-02-28
申请号：US16119487
申请日：2018-08-31
申请人： MIPS Tech, LLC
摘要： A binary logic circuit for manipulating an input binary string includes a first stage of a first group of multiplexers arranged to select respective portions of an input binary string and configured to receive a respective first control. A second stage is included in which a plurality of a second group of multiplexers is arranged to select respective portions of the input binary string and configured to receive a respective second control signal. The control signals are provided such that each multiplexer of a second group is configured to select a respective second portion of the first binary string. Control circuitry is configured to generate the first and second control signals such that two or more of the first groups and/or two or more of the second groups of multiplexers are independently controllable.
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公开(公告)号：US20230237325A1
公开(公告)日：2023-07-27
申请号：US18114044
申请日：2023-02-24
申请人： MIPS Tech, LLC
CPC分类号： G06N3/08 , G06F7/5443 , G06N3/063 , G06F2207/3824 , G06F2207/4824
摘要： Techniques for mixed-precision data manipulation for neural network data computation are disclosed. A first left group comprising eight bytes of data and a first right group of eight bytes of data are obtained for computation using a processor. A second left group comprising eight bytes of data and a second right group of eight bytes of data are obtained. A sum of products is performed between the first left and right groups and the second left and right groups. The sum of products is performed on bytes of 8-bit integer data. A first result is based on a summation of eight values that are products of the first group’s left eight bytes and the second group’s left eight bytes. A second result is based on the summation of eight values that are products of the first group’s left eight bytes and the second group’s right eight bytes. Results are output.
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公开(公告)号：US11645178B2
公开(公告)日：2023-05-09
申请号：US16522429
申请日：2019-07-25
申请人： MIPS Tech, LLC
IPC分类号： G06F11/18 , G06F11/273 , G06F11/22
CPC分类号： G06F11/273 , G06F11/2242
摘要： Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.
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公开(公告)号：US20210373897A1
公开(公告)日：2021-12-02
申请号：US17364718
申请日：2021-06-30
申请人： MIPS Tech, LLC
摘要： Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
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